# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl
# do hc595_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/002\ 74hc595/rtl {F:/Code/FPGA/study/002 74hc595/rtl/hc595.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:58:58 on Oct 04,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/002 74hc595/rtl" F:/Code/FPGA/study/002 74hc595/rtl/hc595.v 
# -- Compiling module hc595
# 
# Top level modules:
# 	hc595
# End time: 21:58:58 on Oct 04,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/002\ 74hc595/prj/../testbench {F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 21:58:58 on Oct 04,2018
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/002 74hc595/prj/../testbench" F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v 
# -- Compiling module hc595_tb
# 
# Top level modules:
# 	hc595_tb
# End time: 21:58:58 on Oct 04,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  hc595_tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" hc595_tb 
# Start time: 21:58:58 on Oct 04,2018
# Loading work.hc595_tb
# Loading work.hc595
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# ** Note: $stop    : F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v(39)
#    Time: 200400 ns  Iteration: 0  Instance: /hc595_tb
# Break in Module hc595_tb at F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v line 39
# End time: 11:26:36 on Oct 05,2018, Elapsed time: 13:27:38
# Errors: 0, Warnings: 0