# -------------------------------------------------------------------------- # # # Copyright (C) 2018 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel FPGA IP License Agreement, or other applicable license # agreement, including, without limitation, that your use is for # the sole purpose of programming logic devices manufactured by # Intel and sold by Intel or its authorized distributors. Please # refer to the applicable agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition # Date created = 19:21:21 November 12, 2018 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # nios_usart_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "Cyclone IV E" set_global_assignment -name DEVICE EP4CE10F17C8 set_global_assignment -name TOP_LEVEL_ENTITY nico_usart set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:21:21 NOVEMBER 12, 2018" set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Standard Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation set_global_assignment -name QSYS_FILE my_cpu.qsys set_global_assignment -name VERILOG_FILE rtl/nico_usart.v set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_0_txd set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tck set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tdi set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tdo set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to altera_reserved_tms set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to key[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to led[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rst_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to uart_0_rxd set_location_assignment PIN_E1 -to clk set_location_assignment PIN_R1 -to key[1] set_location_assignment PIN_P2 -to key[0] set_location_assignment PIN_A3 -to led[3] set_location_assignment PIN_A4 -to led[2] set_location_assignment PIN_B3 -to led[1] set_location_assignment PIN_A2 -to led[0] set_location_assignment PIN_E16 -to rst_n set_location_assignment PIN_B5 -to uart_0_rxd set_location_assignment PIN_A6 -to uart_0_txd set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[11] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[10] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_addr[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ba[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cas_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cke set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_clk set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_cs_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[15] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[14] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[13] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[12] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[11] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[10] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[9] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[8] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[7] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[6] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[5] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[4] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[3] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[2] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dq[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm[1] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_dqm[0] set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_ras_n set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to sdram_we_n set_location_assignment PIN_T9 -to sdram_we_n set_location_assignment PIN_N9 -to sdram_ras_n set_location_assignment PIN_R10 -to sdram_dqm[1] set_location_assignment PIN_T8 -to sdram_dqm[0] set_location_assignment PIN_P9 -to sdram_dq[15] set_location_assignment PIN_N8 -to sdram_dq[14] set_location_assignment PIN_M8 -to sdram_dq[13] set_location_assignment PIN_L8 -to sdram_dq[12] set_location_assignment PIN_K8 -to sdram_dq[11] set_location_assignment PIN_L9 -to sdram_dq[10] set_location_assignment PIN_K9 -to sdram_dq[9] set_location_assignment PIN_R9 -to sdram_dq[8] set_location_assignment PIN_R8 -to sdram_dq[7] set_location_assignment PIN_R6 -to sdram_dq[6] set_location_assignment PIN_T5 -to sdram_dq[5] set_location_assignment PIN_R5 -to sdram_dq[4] set_location_assignment PIN_T4 -to sdram_dq[3] set_location_assignment PIN_R4 -to sdram_dq[2] set_location_assignment PIN_T3 -to sdram_dq[1] set_location_assignment PIN_R3 -to sdram_dq[0] set_location_assignment PIN_R12 -to sdram_cs_n set_location_assignment PIN_T10 -to sdram_clk set_location_assignment PIN_T11 -to sdram_cke set_location_assignment PIN_R11 -to sdram_cas_n set_location_assignment PIN_M9 -to sdram_ba[1] set_location_assignment PIN_T12 -to sdram_ba[0] set_location_assignment PIN_R13 -to sdram_addr[11] set_location_assignment PIN_M10 -to sdram_addr[10] set_location_assignment PIN_T14 -to sdram_addr[9] set_location_assignment PIN_R14 -to sdram_addr[8] set_location_assignment PIN_T15 -to sdram_addr[7] set_location_assignment PIN_L11 -to sdram_addr[6] set_location_assignment PIN_M11 -to sdram_addr[5] set_location_assignment PIN_N12 -to sdram_addr[4] set_location_assignment PIN_T13 -to sdram_addr[3] set_location_assignment PIN_P14 -to sdram_addr[2] set_location_assignment PIN_L10 -to sdram_addr[1] set_location_assignment PIN_P11 -to sdram_addr[0] set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top