module ctrl(
  clk,
  rst_n,
  key_in,
  iIR,
  
  pwm_out,
  SH_CP,
  ST_CP,
  DS
);	

  input clk;
  input rst_n;
  input key_in;
  input iIR;
  
  output  pwm_out;
  
  output SH_CP;	//shift clock
  output ST_CP;	//latch data clock
  output DS;	//shift serial data
  
  wire key_in;
  wire key_state,key_flag;
  wire [15:0] irAddr;
  wire [15:0] irData;
  wire  Get_Flag;
  reg en_pwm;
  reg [25:0] cnt;
  
  reg [31:0] disp_data;
  
  always @ (posedge clk)
    if(!rst_n)
	   disp_data <= 32'd0;
    else if((irData[7:0] < 8'ha) & Get_Flag)
	   disp_data <= {disp_data[27:0],irData[3:0]};
  
  
	   
  
  always @ (posedge clk)
    if(!rst_n)  
      en_pwm <= 1'b0;
	 else if(cnt == 26'd100_00_000)
	   en_pwm <= 1'b0;
	 else if(Get_Flag)
	   en_pwm <= 1'b1;
		
  always @ (posedge clk)
    if(!rst_n)
	   cnt <= 23'd0;
	 else if(en_pwm)
	   cnt <= cnt +23'd1;
	 else
	   cnt <= 23'd0;
  
	 
  key_filter key0(
	.Clk(clk),      //50M时钟输入
	.Rst_n(rst_n),    //模块复位
	.key_in(key_in),   //按键输入
	.key_flag(key_flag), //按键标志信号
	.key_state(key_state)//按键状态信号
	);

  pwm pwm0(
    .clk(clk),
    .rst_n(rst_n),
    .en_pwm(en_pwm),
    .pwm_arr(16'd19000),
    .pwm_ccr(16'd9555),
    .pwm_out(pwm_out)
  
  );
  
  ir_decoder ir0(
	
	.clk(clk),
	.rst_n(rst_n),
	.iIR(iIR),
	.irAddr(irAddr),
	.irData(irData),
	.Get_Flag(Get_Flag)

);

  HEX_top seg0(
  	  .Clk(clk),
  	  .Rst_n(rst_n),
  	  .disp_data(disp_data),
  	  .SH_CP(SH_CP),
  	  .ST_CP(ST_CP),
  	  .DS(DS)
  );


endmodule