# Reading D:/intelFPGA/modelsim_ase/tcl/vsim/pref.tcl
# do uart_tx_run_msim_rtl_verilog.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct  5 2016
# vmap work rtl_work 
# Copying D:/intelFPGA/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# 
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/rtl {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:22:36 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v 
# -- Compiling module uart_tx
# 
# Top level modules:
# 	uart_tx
# End time: 20:22:36 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/rtl {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:22:36 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v 
# -- Compiling module uart_tx_top
# 
# Top level modules:
# 	uart_tx_top
# End time: 20:22:37 on Jan 03,2019, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/ip {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:22:37 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v 
# -- Compiling module ram_uart
# 
# Top level modules:
# 	ram_uart
# End time: 20:22:37 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/testbench {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:22:37 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v 
# -- Compiling module uart_tx_top_tb
# 
# Top level modules:
# 	uart_tx_top_tb
# End time: 20:22:37 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  uart_tx_top_tb
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" uart_tx_top_tb 
# Start time: 20:22:37 on Jan 03,2019
# Loading work.uart_tx_top_tb
# Loading work.uart_tx_top
# Loading work.uart_tx
# Loading work.ram_uart
# Loading altera_mf_ver.altsyncram
# Loading altera_mf_ver.altsyncram_body
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
# ** Note: $stop    : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
#    Time: 10000100 ns  Iteration: 0  Instance: /uart_tx_top_tb
# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
add wave -position insertpoint sim:/uart_tx_top_tb/u0/*
restart
run -all
# GetModuleFileName: 找不到指定的模块。
# 
# 
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
# ** Note: $stop    : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
#    Time: 10000100 ns  Iteration: 0  Instance: /uart_tx_top_tb
# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:27:21 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v 
# -- Compiling module ram_uart
# 
# Top level modules:
# 	ram_uart
# End time: 20:27:21 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:27:21 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v 
# -- Compiling module uart_tx
# 
# Top level modules:
# 	uart_tx
# End time: 20:27:21 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:27:21 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v 
# -- Compiling module uart_tx_top
# 
# Top level modules:
# 	uart_tx_top
# End time: 20:27:22 on Jan 03,2019, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:27:22 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v 
# -- Compiling module uart_tx_top_tb
# 
# Top level modules:
# 	uart_tx_top_tb
# End time: 20:27:22 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:28:01 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v 
# -- Compiling module ram_uart
# 
# Top level modules:
# 	ram_uart
# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:28:01 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v 
# -- Compiling module uart_tx
# 
# Top level modules:
# 	uart_tx
# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:28:01 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v 
# -- Compiling module uart_tx_top
# 
# Top level modules:
# 	uart_tx_top
# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:28:01 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v 
# -- Compiling module uart_tx_top_tb
# 
# Top level modules:
# 	uart_tx_top_tb
# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
run
restart
# Loading work.uart_tx_top_tb
# Loading work.uart_tx_top
# Loading work.uart_tx
# Loading work.ram_uart
run -all
# GetModuleFileName: 找不到指定的模块。
# 
# 
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
# ** Note: $stop    : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
#    Time: 2000100 ns  Iteration: 0  Instance: /uart_tx_top_tb
# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:22 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v 
# -- Compiling module ram_uart
# 
# Top level modules:
# 	ram_uart
# End time: 20:31:22 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:22 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v 
# -- Compiling module uart_tx
# 
# Top level modules:
# 	uart_tx
# End time: 20:31:22 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:23 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v 
# -- Compiling module uart_tx_top
# ** Error: F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v(66): (vlog-2110) Illegal reference to net "endaddress".
# ** Error: F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v(68): (vlog-2110) Illegal reference to net "endaddress".
# End time: 20:31:23 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 2, Warnings: 0
# D:/intelFPGA/modelsim_ase/win32aloem/vlog failed.
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:23 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v 
# -- Compiling module uart_tx_top_tb
# 
# Top level modules:
# 	uart_tx_top_tb
# End time: 20:31:23 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.uart_tx_top_tb
# Loading work.uart_tx
# Loading work.ram_uart
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:51 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v 
# -- Compiling module ram_uart
# 
# Top level modules:
# 	ram_uart
# End time: 20:31:51 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:51 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v 
# -- Compiling module uart_tx
# 
# Top level modules:
# 	uart_tx
# End time: 20:31:51 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:51 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v 
# -- Compiling module uart_tx_top
# 
# Top level modules:
# 	uart_tx_top
# End time: 20:31:52 on Jan 03,2019, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:31:52 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v 
# -- Compiling module uart_tx_top_tb
# 
# Top level modules:
# 	uart_tx_top_tb
# End time: 20:31:52 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.uart_tx_top_tb
# Loading work.uart_tx_top
# Loading work.uart_tx
# Loading work.ram_uart
run -all
# GetModuleFileName: 找不到指定的模块。
# 
# 
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
# ** Note: $stop    : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
#    Time: 2000100 ns  Iteration: 0  Instance: /uart_tx_top_tb
# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:32:40 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v 
# -- Compiling module ram_uart
# 
# Top level modules:
# 	ram_uart
# End time: 20:32:40 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:32:40 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v 
# -- Compiling module uart_tx
# 
# Top level modules:
# 	uart_tx
# End time: 20:32:40 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:32:41 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v 
# -- Compiling module uart_tx_top
# 
# Top level modules:
# 	uart_tx_top
# End time: 20:32:41 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:32:41 on Jan 03,2019
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v 
# -- Compiling module uart_tx_top_tb
# 
# Top level modules:
# 	uart_tx_top_tb
# End time: 20:32:41 on Jan 03,2019, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
restart
# Loading work.uart_tx_top_tb
# Loading work.uart_tx_top
# Loading work.uart_tx
# Loading work.ram_uart
run -all
# GetModuleFileName: 找不到指定的模块。
# 
# 
# Warning: read_during_write_mode_mixed_ports is assumed as               OLD_DATA
# Time: 0  Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
# ** Note: $stop    : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
#    Time: 6000100 ns  Iteration: 0  Instance: /uart_tx_top_tb
# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
# End time: 21:46:51 on Jan 03,2019, Elapsed time: 1:24:14
# Errors: 3, Warnings: 0