14 lines
5.7 KiB
Plaintext
14 lines
5.7 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1548650878142 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1548650878158 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jan 28 12:47:57 2019 " "Processing started: Mon Jan 28 12:47:57 2019" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1548650878158 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1548650878158 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off decoder_138 -c decoder_138 " "Command: quartus_eda --read_settings_files=off --write_settings_files=off decoder_138 -c decoder_138" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1548650878159 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1548650878826 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_8_1200mv_85c_slow.vo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650878985 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_8_1200mv_0c_slow.vo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879005 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_min_1200mv_0c_fast.vo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879039 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138.vo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138.vo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879062 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879086 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879107 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879132 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "decoder_138_v.sdo F:/Code/FPGA/study/decoder/simulation/modelsim/ simulation " "Generated file decoder_138_v.sdo in folder \"F:/Code/FPGA/study/decoder/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1548650879160 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4662 " "Peak virtual memory: 4662 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1548650879203 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jan 28 12:47:59 2019 " "Processing ended: Mon Jan 28 12:47:59 2019" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1548650879203 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1548650879203 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1548650879203 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1548650879203 ""}
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