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study/decoder/simulation/modelsim/decoder_138_run_msim_rtl_verilog.do.bak
2020-06-09 15:48:03 +08:00

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if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/decoder/rtl {F:/Code/FPGA/study/decoder/rtl/decoder_138.v}
vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/decoder/testbench {F:/Code/FPGA/study/decoder/testbench/decoder_138_tb.v}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" decoder_138_tb
add wave *
view structure
view signals
run -all