52 lines
2.4 KiB
Plaintext
52 lines
2.4 KiB
Plaintext
# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl
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# do hc595_run_msim_rtl_verilog.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap work rtl_work
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# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
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# Modifying modelsim.ini
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#
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# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/002\ 74hc595/rtl {F:/Code/FPGA/study/002 74hc595/rtl/hc595.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:58:58 on Oct 04,2018
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/002 74hc595/rtl" F:/Code/FPGA/study/002 74hc595/rtl/hc595.v
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# -- Compiling module hc595
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#
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# Top level modules:
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# hc595
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# End time: 21:58:58 on Oct 04,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/002\ 74hc595/prj/../testbench {F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:58:58 on Oct 04,2018
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/002 74hc595/prj/../testbench" F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v
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# -- Compiling module hc595_tb
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#
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# Top level modules:
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# hc595_tb
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# End time: 21:58:58 on Oct 04,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" hc595_tb
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# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" hc595_tb
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# Start time: 21:58:58 on Oct 04,2018
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# Loading work.hc595_tb
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# Loading work.hc595
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#
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# add wave *
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# view structure
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# .main_pane.structure.interior.cs.body.struct
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# view signals
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# .main_pane.objects.interior.cs.body.tree
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# run -all
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# ** Note: $stop : F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v(39)
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# Time: 200400 ns Iteration: 0 Instance: /hc595_tb
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# Break in Module hc595_tb at F:/Code/FPGA/study/002 74hc595/prj/../testbench/hc595_tb.v line 39
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# End time: 11:26:36 on Oct 05,2018, Elapsed time: 13:27:38
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# Errors: 0, Warnings: 0
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