110 lines
6.1 KiB
Plaintext
110 lines
6.1 KiB
Plaintext
--altsyncram ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" MAXIMUM_DEPTH=0 NUMWORDS_A=256 NUMWORDS_B=256 OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" RAM_BLOCK_TYPE="AUTO" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=2 WIDTH_B=2 WIDTHAD_A=8 WIDTHAD_B=8 address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 18.0 cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M9K 1
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_97d1
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(
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address_a[7..0] : input;
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address_b[7..0] : input;
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clock0 : input;
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data_a[1..0] : input;
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q_b[1..0] : output;
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rden_b : input;
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wren_a : input;
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)
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VARIABLE
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ram_block1a0 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 8,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 255,
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PORT_A_LOGICAL_RAM_DEPTH = 256,
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PORT_A_LOGICAL_RAM_WIDTH = 2,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 8,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 255,
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PORT_B_LOGICAL_RAM_DEPTH = 256,
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PORT_B_LOGICAL_RAM_WIDTH = 2,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : cycloneive_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 8,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 255,
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PORT_A_LOGICAL_RAM_DEPTH = 256,
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PORT_A_LOGICAL_RAM_WIDTH = 2,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 8,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 255,
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PORT_B_LOGICAL_RAM_DEPTH = 256,
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PORT_B_LOGICAL_RAM_WIDTH = 2,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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address_a_wire[7..0] : WIRE;
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address_b_wire[7..0] : WIRE;
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BEGIN
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ram_block1a[1..0].clk0 = clock0;
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ram_block1a[1..0].portaaddr[] = ( address_a_wire[7..0]);
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ram_block1a[0].portadatain[] = ( data_a[0..0]);
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ram_block1a[1].portadatain[] = ( data_a[1..1]);
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ram_block1a[1..0].portawe = wren_a;
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ram_block1a[1..0].portbaddr[] = ( address_b_wire[7..0]);
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ram_block1a[1..0].portbre = rden_b;
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address_a_wire[] = address_a[];
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address_b_wire[] = address_b[];
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q_b[] = ( ram_block1a[1..0].portbdataout[0..0]);
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END;
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--VALID FILE
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