52 lines
36 KiB
Plaintext
52 lines
36 KiB
Plaintext
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1542023228771 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1542023228772 ""}
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{ "Info" "IMPP_MPP_USER_DEVICE" "nios_usart EP4CE10F17C8 " "Selected device EP4CE10F17C8 for design \"nios_usart\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1542023228845 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1542023228916 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1542023228916 ""}
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{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1542023229105 ""}
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{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE6F17C8 " "Device EP4CE6F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1542023229522 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1542023229522 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1542023229522 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1542023229522 ""}
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{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12332 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1542023229534 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12334 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1542023229534 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12336 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1542023229534 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12338 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1542023229534 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ F16 " "Pin ~ALTERA_nCEO~ is reserved at location F16" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12340 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1542023229534 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1542023229534 ""}
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{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1542023229538 ""}
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{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1542023229628 ""}
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{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1542023231235 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1542023231235 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1542023231235 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1542023231235 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1542023231235 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1542023231235 ""}
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{ "Info" "ISTA_SDC_FOUND" "f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.sdc " "Reading SDC File: 'f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1542023231272 ""}
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{ "Info" "ISTA_SDC_FOUND" "f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/my_cpu_nios2_cpu_cpu.sdc " "Reading SDC File: 'f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/my_cpu_nios2_cpu_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Fitter" 0 -1 1542023231282 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|my_cpu_nios2_cpu_cpu_nios2_oci:the_my_cpu_nios2_cpu_cpu_nios2_oci\|my_cpu_nios2_cpu_cpu_nios2_oci_debug:the_my_cpu_nios2_cpu_cpu_nios2_oci_debug\|monitor_ready clk " "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|my_cpu_nios2_cpu_cpu_nios2_oci:the_my_cpu_nios2_cpu_cpu_nios2_oci\|my_cpu_nios2_cpu_cpu_nios2_oci_debug:the_my_cpu_nios2_cpu_cpu_nios2_oci_debug\|monitor_ready is being clocked by clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1542023231343 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1542023231343 "|nico_usart|clk"}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023231389 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023231389 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1542023231389 ""}
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{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1542023231390 ""}
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{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1542023231390 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1542023231390 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1542023231390 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1542023231390 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} } { { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 10 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12322 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1542023231998 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} } { { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 11967 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1542023231998 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_n~input (placed in PIN E16 (CLK5, DIFFCLK_2n)) " "Automatically promoted node rst_n~input (placed in PIN E16 (CLK5, DIFFCLK_2n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G7 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G7" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "my_cpu:u0\|altera_reset_controller:rst_controller\|merged_reset~0 " "Destination node my_cpu:u0\|altera_reset_controller:rst_controller\|merged_reset~0" { } { { "db/ip/my_cpu/submodules/altera_reset_controller.v" "" { Text "F:/Code/FPGA/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.v" 134 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 6993 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1542023231998 ""} } { { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 11 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 12323 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1542023231998 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_cpu:u0\|altera_reset_controller:rst_controller_001\|r_sync_rst " "Automatically promoted node my_cpu:u0\|altera_reset_controller:rst_controller_001\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "my_cpu:u0\|altera_reset_controller:rst_controller_001\|WideOr0~0 " "Destination node my_cpu:u0\|altera_reset_controller:rst_controller_001\|WideOr0~0" { } { { "db/ip/my_cpu/submodules/altera_reset_controller.v" "" { Text "F:/Code/FPGA/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.v" 290 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 5167 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|my_cpu_nios2_cpu_cpu_nios2_oci:the_my_cpu_nios2_cpu_cpu_nios2_oci\|my_cpu_nios2_cpu_cpu_nios2_oci_debug:the_my_cpu_nios2_cpu_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1 " "Destination node my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|my_cpu_nios2_cpu_cpu_nios2_oci:the_my_cpu_nios2_cpu_cpu_nios2_oci\|my_cpu_nios2_cpu_cpu_nios2_oci_debug:the_my_cpu_nios2_cpu_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1" { } { { "altera_std_synchronizer.v" "" { Text "d:/intelfpga/18.0/quartus/libraries/megafunctions/altera_std_synchronizer.v" 45 -1 0 } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|my_cpu_nios2_cpu_cpu_nios2_oci:the_my_cpu_nios2_cpu_cpu_nios2_oci\|my_cpu_nios2_cpu_cpu_nios2_oci_debug:the_my_cpu_nios2_cpu_cpu_nios2_oci_debug\|altera_std_synchronizer:the_altera_std_synchronizer\|din_s1" } } } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 1406 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1542023231998 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1542023231998 ""} } { { "db/ip/my_cpu/submodules/altera_reset_controller.v" "" { Text "F:/Code/FPGA/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.v" 288 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 516 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1542023231998 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_cpu:u0\|altera_reset_controller:rst_controller\|r_sync_rst " "Automatically promoted node my_cpu:u0\|altera_reset_controller:rst_controller\|r_sync_rst " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1542023231999 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "my_cpu:u0\|altera_reset_controller:rst_controller\|WideOr0~0 " "Destination node my_cpu:u0\|altera_reset_controller:rst_controller\|WideOr0~0" { } { { "db/ip/my_cpu/submodules/altera_reset_controller.v" "" { Text "F:/Code/FPGA/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.v" 290 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 4973 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1542023231999 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1542023231999 ""} } { { "db/ip/my_cpu/submodules/altera_reset_controller.v" "" { Text "F:/Code/FPGA/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.v" 288 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 539 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1542023231999 ""}
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{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "my_cpu:u0\|altera_reset_controller:rst_controller\|merged_reset~0 " "Automatically promoted node my_cpu:u0\|altera_reset_controller:rst_controller\|merged_reset~0 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1542023231999 ""} } { { "db/ip/my_cpu/submodules/altera_reset_controller.v" "" { Text "F:/Code/FPGA/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.v" 134 -1 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 6993 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1542023231999 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1542023232723 ""}
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{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1542023232730 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1542023232731 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1542023232741 ""}
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{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1542023232752 ""}
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{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1542023232763 ""}
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{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1542023232930 ""}
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{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "2 Block RAM " "Packed 2 registers into blocks of type Block RAM" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1542023232937 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "48 Embedded multiplier block " "Packed 48 registers into blocks of type Embedded multiplier block" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1542023232937 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "64 Embedded multiplier output " "Packed 64 registers into blocks of type Embedded multiplier output" { } { } 1 176218 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "Design Software" 0 -1 1542023232937 ""} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "48 " "Created 48 register duplicates" { } { } 1 176220 "Created %1!d! register duplicates" 0 0 "Design Software" 0 -1 1542023232937 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1542023232937 ""}
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{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:04 " "Fitter preparation operations ending: elapsed time is 00:00:04" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1542023233131 ""}
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{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1542023233141 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1542023234081 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1542023234824 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1542023234884 ""}
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{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1542023235949 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1542023235949 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1542023236912 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "13 " "Router estimated average interconnect usage is 13% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "27 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 1 { 0 "Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1542023238567 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1542023238567 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1542023239109 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1542023239109 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1542023239109 ""}
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{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1542023239113 ""}
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{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.54 " "Total time spent on timing analysis during the Fitter is 0.54 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1542023239361 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1542023239403 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1542023239962 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1542023239965 ""}
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|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1542023240672 ""}
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{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1542023241646 ""}
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{ "Warning" "WFIOMGR_FIOMGR_REFER_APPNOTE_447_TOP_LEVEL" "9 Cyclone IV E " "9 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone IV E Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." { { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "led\[0\] 3.3-V LVTTL A2 " "Pin led\[0\] uses I/O standard 3.3-V LVTTL at A2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { led[0] } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[0\]" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 450 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "led\[1\] 3.3-V LVTTL B3 " "Pin led\[1\] uses I/O standard 3.3-V LVTTL at B3" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { led[1] } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[1\]" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 451 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "led\[2\] 3.3-V LVTTL A4 " "Pin led\[2\] uses I/O standard 3.3-V LVTTL at A4" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { led[2] } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[2\]" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 452 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "led\[3\] 3.3-V LVTTL A3 " "Pin led\[3\] uses I/O standard 3.3-V LVTTL at A3" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { led[3] } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "led\[3\]" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 12 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 453 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "key\[0\] 3.3-V LVTTL P2 " "Pin key\[0\] uses I/O standard 3.3-V LVTTL at P2" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { key[0] } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "key\[0\]" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 13 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 454 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "key\[1\] 3.3-V LVTTL R1 " "Pin key\[1\] uses I/O standard 3.3-V LVTTL at R1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { key[1] } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "key\[1\]" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 13 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 455 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "clk 3.3-V LVTTL E1 " "Pin clk uses I/O standard 3.3-V LVTTL at E1" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { clk } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "clk" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 10 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 456 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "rst_n 3.3-V LVTTL E16 " "Pin rst_n uses I/O standard 3.3-V LVTTL at E16" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { rst_n } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "rst_n" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 11 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 457 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} { "Info" "IFIOMGR_PIN_IO_STANDARD_LOCATION" "uart_0_rxd 3.3-V LVTTL B5 " "Pin uart_0_rxd uses I/O standard 3.3-V LVTTL at B5" { } { { "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga/18.0/quartus/bin64/pin_planner.ppl" { uart_0_rxd } } } { "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" "" { Assignment "d:/intelfpga/18.0/quartus/bin64/Assignment Editor.qase" 1 { { 0 "uart_0_rxd" } } } } { "rtl/nico_usart.v" "" { Text "F:/Code/FPGA/study/nios_usart/rtl/nico_usart.v" 15 0 0 } } { "temporary_test_loc" "" { Generic "F:/Code/FPGA/study/nios_usart/" { { 0 { 0 ""} 0 458 14177 15141 0 0 "" 0 "" "" } } } } } 0 169178 "Pin %1!s! uses I/O standard %2!s! at %3!s!" 0 0 "Design Software" 0 -1 1542023242047 ""} } { } 0 169177 "%1!d! pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing %2!s! Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems." 0 0 "Fitter" 0 -1 1542023242047 ""}
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|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/Code/FPGA/study/nios_usart/output_files/nios_usart.fit.smsg " "Generated suppressed messages file F:/Code/FPGA/study/nios_usart/output_files/nios_usart.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1542023242356 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 7 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5629 " "Peak virtual memory: 5629 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1542023243797 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 12 19:47:23 2018 " "Processing ended: Mon Nov 12 19:47:23 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1542023243797 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:16 " "Elapsed time: 00:00:16" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1542023243797 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:21 " "Total CPU time (on all processors): 00:00:21" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1542023243797 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1542023243797 ""}
|