45 lines
30 KiB
Plaintext
45 lines
30 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1542023249710 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1542023249729 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 12 19:47:29 2018 " "Processing started: Mon Nov 12 19:47:29 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1542023249729 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1542023249729 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta nios_usart -c nios_usart " "Command: quartus_sta nios_usart -c nios_usart" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1542023249729 ""}
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{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1542023249965 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1542023250365 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1542023250365 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023250439 ""}
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{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023250439 ""}
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{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "altera_std_synchronizer " "Entity altera_std_synchronizer" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\] " "set_false_path -to \[get_keepers \{*altera_std_synchronizer:*\|din_s1\}\]" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1542023250959 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1542023250959 ""} { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1542023250959 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1542023250959 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1542023250959 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Timing Analyzer" 0 -1 1542023250959 ""}
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{ "Info" "ISTA_SDC_FOUND" "f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.sdc " "Reading SDC File: 'f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/altera_reset_controller.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1542023250986 ""}
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{ "Info" "ISTA_SDC_FOUND" "f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/my_cpu_nios2_cpu_cpu.sdc " "Reading SDC File: 'f:/code/fpga/study/nios_usart/db/ip/my_cpu/submodules/my_cpu_nios2_cpu_cpu.sdc'" { } { } 0 332104 "Reading SDC File: '%1!s!'" 0 0 "Timing Analyzer" 0 -1 1542023250998 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|W_debug_mode clk " "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|W_debug_mode is being clocked by clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1542023251035 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1542023251035 "|nico_usart|clk"}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023251070 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023251070 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1542023251070 ""}
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{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1542023251071 ""}
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{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1542023251103 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.018 " "Worst-case setup slack is 46.018" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251147 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251147 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.018 0.000 altera_reserved_tck " " 46.018 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251147 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023251147 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251154 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251154 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 altera_reserved_tck " " 0.452 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251154 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023251154 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 96.537 " "Worst-case recovery slack is 96.537" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251160 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 96.537 0.000 altera_reserved_tck " " 96.537 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251160 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023251160 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.613 " "Worst-case removal slack is 1.613" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251165 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.613 0.000 altera_reserved_tck " " 1.613 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251165 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023251165 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.456 " "Worst-case minimum pulse width slack is 49.456" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251168 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.456 0.000 altera_reserved_tck " " 49.456 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023251168 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023251168 ""}
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{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 196.767 ns " "Worst Case Available Settling Time: 196.767 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023251232 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1542023251232 ""}
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{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1542023251239 ""}
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{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1542023251283 ""}
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{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1542023252334 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|W_debug_mode clk " "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|W_debug_mode is being clocked by clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1542023252672 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1542023252672 "|nico_usart|clk"}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023252679 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023252679 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1542023252679 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 46.353 " "Worst-case setup slack is 46.353" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 46.353 0.000 altera_reserved_tck " " 46.353 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252695 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023252695 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.401 " "Worst-case hold slack is 0.401" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252702 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252702 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.401 0.000 altera_reserved_tck " " 0.401 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252702 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023252702 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 96.717 " "Worst-case recovery slack is 96.717" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252707 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 96.717 0.000 altera_reserved_tck " " 96.717 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252707 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023252707 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.451 " "Worst-case removal slack is 1.451" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252712 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.451 0.000 altera_reserved_tck " " 1.451 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252712 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023252712 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.325 " "Worst-case minimum pulse width slack is 49.325" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252715 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.325 0.000 altera_reserved_tck " " 49.325 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023252715 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023252715 ""}
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{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 197.015 ns " "Worst Case Available Settling Time: 197.015 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023252766 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1542023252766 ""}
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{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1542023252773 ""}
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{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "clk " "Node: clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|W_debug_mode clk " "Register my_cpu:u0\|my_cpu_nios2_cpu:nios2_cpu\|my_cpu_nios2_cpu_cpu:cpu\|W_debug_mode is being clocked by clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1542023253078 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1542023253078 "|nico_usart|clk"}
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{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023253086 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1542023253086 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1542023253086 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "setup 48.518 " "Worst-case setup slack is 48.518" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253099 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253099 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 48.518 0.000 altera_reserved_tck " " 48.518 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253099 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023253099 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253107 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253107 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 altera_reserved_tck " " 0.186 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253107 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023253107 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 98.376 " "Worst-case recovery slack is 98.376" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253114 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253114 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.376 0.000 altera_reserved_tck " " 98.376 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253114 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023253114 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.670 " "Worst-case removal slack is 0.670" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253120 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.670 0.000 altera_reserved_tck " " 0.670 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253120 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023253120 ""}
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{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.294 " "Worst-case minimum pulse width slack is 49.294" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253126 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.294 0.000 altera_reserved_tck " " 49.294 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1542023253126 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1542023253126 ""}
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{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 3 synchronizer chains. " "Report Metastability: Found 3 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n " "Typical MTBF of Design is 1e+09 years or 3.15e+16 seconds.\n" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 3 " "Number of Synchronizer Chains Found: 3" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 2 Registers " "Shortest Synchronizer Chain: 2 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333 " "Fraction of Chains for which MTBFs Could Not be Calculated: 0.333" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 198.630 ns " "Worst Case Available Settling Time: 198.630 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions. " "Typical MTBF values are calculated based on the nominal silicon characteristics, at nominal operating conditions." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8 " " - Under typical conditions, an increase of 100ps in available settling time will increase MTBF values by a factor of 10.8" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1542023253195 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1542023253195 ""}
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{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1542023253649 ""}
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{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1542023253650 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 13 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4822 " "Peak virtual memory: 4822 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1542023253760 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 12 19:47:33 2018 " "Processing ended: Mon Nov 12 19:47:33 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1542023253760 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1542023253760 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1542023253760 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1542023253760 ""}
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