122 lines
11 KiB
Plaintext
122 lines
11 KiB
Plaintext
Info: Starting: Create block symbol file (.bsf)
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Info: qsys-generate F:\Code\FPGA\study\nios_usart\my_cpu.qsys --block-symbol-file --output-directory=F:\Code\FPGA\study\nios_usart\my_cpu --family="Cyclone IV E" --part=EP4CE10F17C8
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Progress: Loading nios_usart/my_cpu.qsys
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Progress: Reading input file
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Progress: Adding P0 [altera_avalon_pio 18.0]
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Progress: Parameterizing module P0
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Progress: Adding clk_0 [clock_source 18.0]
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Progress: Parameterizing module clk_0
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Progress: Adding cpu_id [altera_avalon_sysid_qsys 18.0]
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Progress: Parameterizing module cpu_id
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Progress: Adding nios2_cpu [altera_nios2_gen2 18.0]
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Progress: Parameterizing module nios2_cpu
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Progress: Adding ram [altera_avalon_onchip_memory2 18.0]
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Progress: Parameterizing module ram
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Progress: Adding rom [altera_avalon_onchip_memory2 18.0]
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Progress: Parameterizing module rom
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: my_cpu.P0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: my_cpu.cpu_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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Info: my_cpu.cpu_id: Time stamp will be automatically updated when this component is generated.
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Info: qsys-generate succeeded.
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Info: Finished: Create block symbol file (.bsf)
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Info:
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Info: Starting: Create HDL design files for synthesis
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Info: qsys-generate F:\Code\FPGA\study\nios_usart\my_cpu.qsys --synthesis=VERILOG --output-directory=F:\Code\FPGA\study\nios_usart\my_cpu\synthesis --family="Cyclone IV E" --part=EP4CE10F17C8
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Progress: Loading nios_usart/my_cpu.qsys
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Progress: Reading input file
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Progress: Adding P0 [altera_avalon_pio 18.0]
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Progress: Parameterizing module P0
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Progress: Adding clk_0 [clock_source 18.0]
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Progress: Parameterizing module clk_0
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Progress: Adding cpu_id [altera_avalon_sysid_qsys 18.0]
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Progress: Parameterizing module cpu_id
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Progress: Adding nios2_cpu [altera_nios2_gen2 18.0]
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Progress: Parameterizing module nios2_cpu
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Progress: Adding ram [altera_avalon_onchip_memory2 18.0]
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Progress: Parameterizing module ram
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Progress: Adding rom [altera_avalon_onchip_memory2 18.0]
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Progress: Parameterizing module rom
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Progress: Building connections
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Progress: Parameterizing connections
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Progress: Validating
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Progress: Done reading input file
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Info: my_cpu.P0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: my_cpu.cpu_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
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Info: my_cpu.cpu_id: Time stamp will be automatically updated when this component is generated.
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Info: my_cpu: Generating my_cpu "my_cpu" for QUARTUS_SYNTH
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Info: P0: Starting RTL generation for module 'my_cpu_P0'
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Info: P0: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=my_cpu_P0 --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0002_P0_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0002_P0_gen//my_cpu_P0_component_configuration.pl --do_build_sim=0 ]
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Info: P0: Done RTL generation for module 'my_cpu_P0'
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Info: P0: "my_cpu" instantiated altera_avalon_pio "P0"
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Info: cpu_id: "my_cpu" instantiated altera_avalon_sysid_qsys "cpu_id"
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Info: nios2_cpu: "my_cpu" instantiated altera_nios2_gen2 "nios2_cpu"
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Info: ram: Starting RTL generation for module 'my_cpu_ram'
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Info: ram: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=my_cpu_ram --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0004_ram_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0004_ram_gen//my_cpu_ram_component_configuration.pl --do_build_sim=0 ]
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Info: ram: Done RTL generation for module 'my_cpu_ram'
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Info: ram: "my_cpu" instantiated altera_avalon_onchip_memory2 "ram"
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Info: rom: Starting RTL generation for module 'my_cpu_rom'
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Info: rom: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=my_cpu_rom --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0005_rom_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0005_rom_gen//my_cpu_rom_component_configuration.pl --do_build_sim=0 ]
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Info: rom: Done RTL generation for module 'my_cpu_rom'
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Info: rom: "my_cpu" instantiated altera_avalon_onchip_memory2 "rom"
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
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Info: mm_interconnect_0: "my_cpu" instantiated altera_mm_interconnect "mm_interconnect_0"
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Info: irq_mapper: "my_cpu" instantiated altera_irq_mapper "irq_mapper"
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Info: rst_controller: "my_cpu" instantiated altera_reset_controller "rst_controller"
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Info: cpu: Starting RTL generation for module 'my_cpu_nios2_cpu_cpu'
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Info: cpu: Generation command is [exec D:/intelFPGA/18.0/quartus/bin64//eperlcmd.exe -I D:/intelFPGA/18.0/quartus/bin64//perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=my_cpu_nios2_cpu_cpu --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0008_cpu_gen/ --quartus_bindir=D:/intelFPGA/18.0/quartus/bin64/ --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0008_cpu_gen//my_cpu_nios2_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]
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Info: cpu: # 2018.11.12 19:22:46 (*) Starting Nios II generation
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Info: cpu: # 2018.11.12 19:22:46 (*) Checking for plaintext license.
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Info: cpu: # 2018.11.12 19:22:47 (*) Plaintext license not found.
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Info: cpu: # 2018.11.12 19:22:47 (*) Checking for encrypted license (non-evaluation).
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Info: cpu: # 2018.11.12 19:22:48 (*) Encrypted license found. SOF will not be time-limited.
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Info: cpu: # 2018.11.12 19:22:48 (*) Elaborating CPU configuration settings
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Info: cpu: # 2018.11.12 19:22:48 (*) Creating all objects for CPU
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Info: cpu: # 2018.11.12 19:22:48 (*) Testbench
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Info: cpu: # 2018.11.12 19:22:49 (*) Instruction decoding
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Info: cpu: # 2018.11.12 19:22:49 (*) Instruction fields
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Info: cpu: # 2018.11.12 19:22:49 (*) Instruction decodes
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Info: cpu: # 2018.11.12 19:22:49 (*) Signals for RTL simulation waveforms
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Info: cpu: # 2018.11.12 19:22:49 (*) Instruction controls
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Info: cpu: # 2018.11.12 19:22:49 (*) Pipeline frontend
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Info: cpu: # 2018.11.12 19:22:49 (*) Pipeline backend
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Info: cpu: # 2018.11.12 19:22:52 (*) Generating RTL from CPU objects
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Info: cpu: # 2018.11.12 19:22:54 (*) Creating encrypted RTL
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Info: cpu: # 2018.11.12 19:22:55 (*) Done Nios II generation
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Info: cpu: Done RTL generation for module 'my_cpu_nios2_cpu_cpu'
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Info: cpu: "nios2_cpu" instantiated altera_nios2_gen2_unit "cpu"
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Info: nios2_cpu_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_cpu_data_master_translator"
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Info: cpu_id_control_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "cpu_id_control_slave_translator"
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Info: nios2_cpu_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_cpu_data_master_agent"
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Info: cpu_id_control_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "cpu_id_control_slave_agent"
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Info: cpu_id_control_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "cpu_id_control_slave_agent_rsp_fifo"
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Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
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Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
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Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
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Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
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Info: nios2_cpu_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_cpu_data_master_limiter"
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Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_avalon_sc_fifo.v
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Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
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Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
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Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
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Info: cmd_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_001"
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Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
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Info: rsp_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_001"
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Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
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Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
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Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_merlin_arbitrator.sv
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Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
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Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
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Info: my_cpu: Done "my_cpu" with 30 modules, 51 files
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Info: qsys-generate succeeded.
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Info: Finished: Create HDL design files for synthesis
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