20 lines
830 B
VHDL
20 lines
830 B
VHDL
component my_cpu is
|
|
port (
|
|
clk_clk : in std_logic := 'X'; -- clk
|
|
led_export : inout std_logic_vector(5 downto 0) := (others => 'X'); -- export
|
|
reset_reset_n : in std_logic := 'X'; -- reset_n
|
|
uart_0_rxd : in std_logic := 'X'; -- rxd
|
|
uart_0_txd : out std_logic -- txd
|
|
);
|
|
end component my_cpu;
|
|
|
|
u0 : component my_cpu
|
|
port map (
|
|
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
|
|
led_export => CONNECTED_TO_led_export, -- led.export
|
|
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
|
|
uart_0_rxd => CONNECTED_TO_uart_0_rxd, -- uart_0.rxd
|
|
uart_0_txd => CONNECTED_TO_uart_0_txd -- .txd
|
|
);
|
|
|