30 lines
426 B
Verilog
30 lines
426 B
Verilog
module nico_usart(
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clk,
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rst_n,
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led,
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key,
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uart_0_rxd,
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uart_0_txd
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);
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input clk;
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input rst_n;
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inout [3:0] led;
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inout [1:0] key;
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input uart_0_rxd;
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output uart_0_txd;
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my_cpu u0 (
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.clk_clk (clk), // clk.clk
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.led_export ({key,led}), // led.export
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.reset_reset_n (rst_n), // reset.reset_n
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.uart_0_rxd (uart_0_rxd),
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.uart_0_txd (uart_0_txd)
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);
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endmodule
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