100 lines
1.5 KiB
Verilog
100 lines
1.5 KiB
Verilog
module ctrl(
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clk,
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rst_n,
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key_in,
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iIR,
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pwm_out,
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SH_CP,
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ST_CP,
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DS
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);
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input clk;
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input rst_n;
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input key_in;
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input iIR;
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output pwm_out;
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output SH_CP; //shift clock
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output ST_CP; //latch data clock
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output DS; //shift serial data
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wire key_in;
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wire key_state,key_flag;
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wire [15:0] irAddr;
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wire [15:0] irData;
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wire Get_Flag;
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reg en_pwm;
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reg [25:0] cnt;
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reg [31:0] disp_data;
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always @ (posedge clk)
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if(!rst_n)
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disp_data <= 32'd0;
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else if((irData[7:0] < 8'ha) & Get_Flag)
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disp_data <= {disp_data[27:0],irData[3:0]};
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always @ (posedge clk)
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if(!rst_n)
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en_pwm <= 1'b0;
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else if(cnt == 26'd100_00_000)
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en_pwm <= 1'b0;
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else if(Get_Flag)
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en_pwm <= 1'b1;
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always @ (posedge clk)
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if(!rst_n)
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cnt <= 23'd0;
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else if(en_pwm)
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cnt <= cnt +23'd1;
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else
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cnt <= 23'd0;
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key_filter key0(
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.Clk(clk), //50M时钟输入
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.Rst_n(rst_n), //模块复位
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.key_in(key_in), //按键输入
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.key_flag(key_flag), //按键标志信号
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.key_state(key_state)//按键状态信号
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);
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pwm pwm0(
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.clk(clk),
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.rst_n(rst_n),
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.en_pwm(en_pwm),
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.pwm_arr(16'd19000),
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.pwm_ccr(16'd9555),
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.pwm_out(pwm_out)
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);
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ir_decoder ir0(
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.clk(clk),
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.rst_n(rst_n),
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.iIR(iIR),
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.irAddr(irAddr),
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.irData(irData),
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.Get_Flag(Get_Flag)
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);
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HEX_top seg0(
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.Clk(clk),
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.Rst_n(rst_n),
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.disp_data(disp_data),
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.SH_CP(SH_CP),
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.ST_CP(ST_CP),
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.DS(DS)
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);
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endmodule
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