191 lines
3.3 KiB
Verilog
191 lines
3.3 KiB
Verilog
`timescale 1ns/1ns
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module ir_decoder(
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clk,
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rst_n,
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iIR,
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irAddr,
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irData,
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Get_Flag
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);
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localparam s0= 3'b000,
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s1= 3'b001,
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s2= 3'b011,
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s3= 3'b010;
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input clk;
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input rst_n;
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input iIR;
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output [15:0] irAddr;
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output [15:0] irData;
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output Get_Flag;
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reg[18:0]cnt;
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reg [2:0]iIR_r;
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reg en;
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reg [2:0]staus,next_status;
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reg [5:0]data_cnt;
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reg [31:0]data_tmp;
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reg Get_Data_Done;
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reg T9ms_ok,T4_5ms_ok,T_56ms_ok,T1_69ms_ok;
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wire pedge,nedge;
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assign nedge = iIR_r[2] & (!iIR_r[1]);
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assign pedge = iIR_r[1] & (!iIR_r[2]);
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assign irAddr = data_tmp[15:0];
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assign irData = data_tmp[31:16];
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assign Get_Flag = Get_Data_Done;
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always @ (posedge clk)
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if(!rst_n)
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begin
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Get_Data_Done <= 1'b0;
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data_cnt <= 6'd0;
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data_tmp <= 32'd0;
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end
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else if(staus == s3)
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if(pedge & (data_cnt == 6'd32))
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begin
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data_cnt <= 6'd0;
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Get_Data_Done <= 1'd1;
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end
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else
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begin
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Get_Data_Done <= 1'd0;
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if(nedge)
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begin
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data_cnt <= data_cnt + 6'd1;
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if(T_56ms_ok)
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data_tmp[data_cnt] <= 1'b0;
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else if(T1_69ms_ok)
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data_tmp[data_cnt] <= 1'b1;
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end
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end
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always @ (posedge clk or negedge rst_n)
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if(!rst_n)
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staus <= s0;//空闲
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else
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staus <= next_status;
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always @ (*)
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case(staus)
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s0:
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if(nedge)
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next_status <= s1;
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else
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next_status <= s0;
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s1:
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if(pedge)
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begin
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if(T9ms_ok)
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next_status <= s2;
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else
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next_status <= s0;
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end
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else
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next_status <= s1;
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s2:
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if(nedge)
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begin
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if(T4_5ms_ok)
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next_status <= s3;
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else
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next_status <= s0;
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end
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else
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next_status <= s2;
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s3:
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if(pedge & (!T_56ms_ok))
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next_status <= s0;
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else if(nedge & (!T_56ms_ok) & (!T1_69ms_ok))
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next_status <= s0;
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else if(Get_Data_Done)
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next_status <= s0;
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else
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next_status <= s3;
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default:next_status<=s0;
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endcase
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always @ (*)
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case(staus)
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s0:
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if(nedge)
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en <= 1'b1;
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else
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en <= 1'b0;
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s1:
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if(pedge & T9ms_ok)
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en <= 1'b0;
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else
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en <= 1'b1;
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s2:
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if(nedge & T4_5ms_ok)
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en <= 1'b0;
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else
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en <= 1'b1;
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s3:
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if(pedge & T_56ms_ok)
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en <= 1'b0;
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else if(nedge & (T_56ms_ok | T1_69ms_ok))
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en <= 1'b0;
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else
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en <= 1'b1;
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default:en<=1'b0;
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endcase
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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T9ms_ok <= 1'b0;
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else if(cnt > 19'd325000 && cnt <19'd495000)
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T9ms_ok <= 1'b1;
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else
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T9ms_ok <= 1'b0;
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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T4_5ms_ok <= 1'b0;
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else if(cnt > 19'd152500 && cnt <19'd277500)
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T4_5ms_ok <= 1'b1;
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else
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T4_5ms_ok <= 1'b0;
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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T_56ms_ok <= 1'b0;
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else if(cnt > 19'd20000 && cnt <19'd35000)
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T_56ms_ok <= 1'b1;
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else
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T_56ms_ok <= 1'b0;
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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T1_69ms_ok <= 1'b0;
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else if(cnt > 19'd75000 && cnt <19'd90000)
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T1_69ms_ok <= 1'b1;
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else
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T1_69ms_ok <= 1'b0;
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always @ (posedge clk)
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if(!rst_n)
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iIR_r <= 3'b111;
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else
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iIR_r <= {iIR_r[1:0],iIR};
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always @ (posedge clk)
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if(!rst_n)
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cnt <= 19'd0;
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else if(en)
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cnt <= cnt+19'd1;
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else
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cnt <= 19'd0;
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endmodule
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