57 lines
933 B
Verilog
57 lines
933 B
Verilog
module uart_tx_top(
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clk,
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rst_n,
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tx
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);
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input clk;
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input rst_n;
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output tx;
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wire tx_done;
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reg [7:0] data;
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reg [4:0] str_cnt;
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uart_tx uart0 (
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.baud_set(2'b00),
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.clk(clk),
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.tx_data(data),
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.en(1'b1),
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.rst_n(rst_n),
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.tx(tx),
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.tx_done(tx_done)
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);
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always @ (posedge clk or negedge rst_n)
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if(!rst_n)
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str_cnt <= 4'd0;
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else if(str_cnt == 13)
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str_cnt <= 4'd0;
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else if(tx_done)
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str_cnt <= str_cnt + 4'd1;
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always @ (posedge clk or negedge rst_n)
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if(!rst_n)
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data <=8'hff;
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else if(tx_done)
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case(str_cnt)
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4'd00 : data <= "H";
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4'd01 : data <= "e";
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4'd02 : data <= "l";
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4'd03 : data <= "l";
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4'd04 : data <= "o";
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4'd05 : data <= " ";
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4'd06 : data <= "F";
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4'd07 : data <= "P";
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4'd08 : data <= "G";
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4'd09 : data <= "A";
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4'd10 : data <= ".";
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4'd11 : data <= "\r";
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4'd12 : data <= "\n";
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default: data <= 8'hff;
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endcase
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endmodule |