338 lines
18 KiB
Plaintext
338 lines
18 KiB
Plaintext
# Reading D:/intelFPGA/modelsim_ase/tcl/vsim/pref.tcl
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# do uart_tx_run_msim_rtl_verilog.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap work rtl_work
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# Copying D:/intelFPGA/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
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# Modifying modelsim.ini
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#
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# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/rtl {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:22:36 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v
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# -- Compiling module uart_tx
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#
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# Top level modules:
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# uart_tx
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# End time: 20:22:36 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/rtl {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:22:36 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v
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# -- Compiling module uart_tx_top
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#
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# Top level modules:
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# uart_tx_top
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# End time: 20:22:37 on Jan 03,2019, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/ip {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:22:37 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v
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# -- Compiling module ram_uart
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#
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# Top level modules:
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# ram_uart
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# End time: 20:22:37 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# vlog -vlog01compat -work work +incdir+F:/Code/FPGA/study/uart_tx\ _cpoy/testbench {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:22:37 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v
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# -- Compiling module uart_tx_top_tb
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#
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# Top level modules:
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# uart_tx_top_tb
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# End time: 20:22:37 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc" uart_tx_top_tb
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# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs=""+acc"" uart_tx_top_tb
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# Start time: 20:22:37 on Jan 03,2019
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# Loading work.uart_tx_top_tb
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# Loading work.uart_tx_top
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# Loading work.uart_tx
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# Loading work.ram_uart
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# Loading altera_mf_ver.altsyncram
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# Loading altera_mf_ver.altsyncram_body
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# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
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# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
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#
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# add wave *
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# view structure
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# .main_pane.structure.interior.cs.body.struct
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# view signals
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# .main_pane.objects.interior.cs.body.tree
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# run -all
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# Warning: read_during_write_mode_mixed_ports is assumed as OLD_DATA
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# Time: 0 Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
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# ** Note: $stop : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
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# Time: 10000100 ns Iteration: 0 Instance: /uart_tx_top_tb
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# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
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add wave -position insertpoint sim:/uart_tx_top_tb/u0/*
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restart
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run -all
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# GetModuleFileName: <20>Ҳ<EFBFBD><D2B2><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ģ<EFBFBD>顣
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#
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#
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# Warning: read_during_write_mode_mixed_ports is assumed as OLD_DATA
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# Time: 0 Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
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# ** Note: $stop : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
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# Time: 10000100 ns Iteration: 0 Instance: /uart_tx_top_tb
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# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:27:21 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v
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# -- Compiling module ram_uart
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#
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# Top level modules:
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# ram_uart
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# End time: 20:27:21 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:27:21 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v
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# -- Compiling module uart_tx
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#
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# Top level modules:
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# uart_tx
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# End time: 20:27:21 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:27:21 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v
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# -- Compiling module uart_tx_top
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#
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# Top level modules:
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# uart_tx_top
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# End time: 20:27:22 on Jan 03,2019, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:27:22 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v
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# -- Compiling module uart_tx_top_tb
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#
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# Top level modules:
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# uart_tx_top_tb
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# End time: 20:27:22 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:28:01 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v
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# -- Compiling module ram_uart
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#
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# Top level modules:
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# ram_uart
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# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:28:01 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v
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# -- Compiling module uart_tx
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#
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# Top level modules:
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# uart_tx
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# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:28:01 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v
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# -- Compiling module uart_tx_top
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#
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# Top level modules:
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# uart_tx_top
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# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:28:01 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v
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# -- Compiling module uart_tx_top_tb
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#
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# Top level modules:
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# uart_tx_top_tb
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# End time: 20:28:01 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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run
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restart
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# Loading work.uart_tx_top_tb
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# Loading work.uart_tx_top
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# Loading work.uart_tx
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# Loading work.ram_uart
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run -all
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# GetModuleFileName: <20>Ҳ<EFBFBD><D2B2><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ģ<EFBFBD>顣
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#
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#
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# Warning: read_during_write_mode_mixed_ports is assumed as OLD_DATA
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# Time: 0 Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
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# ** Note: $stop : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
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# Time: 2000100 ns Iteration: 0 Instance: /uart_tx_top_tb
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# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:22 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v
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# -- Compiling module ram_uart
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#
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# Top level modules:
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# ram_uart
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# End time: 20:31:22 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:22 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v
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# -- Compiling module uart_tx
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#
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# Top level modules:
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# uart_tx
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# End time: 20:31:22 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:23 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v
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# -- Compiling module uart_tx_top
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# ** Error: F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v(66): (vlog-2110) Illegal reference to net "endaddress".
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# ** Error: F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v(68): (vlog-2110) Illegal reference to net "endaddress".
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# End time: 20:31:23 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 2, Warnings: 0
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# D:/intelFPGA/modelsim_ase/win32aloem/vlog failed.
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:23 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v
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# -- Compiling module uart_tx_top_tb
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#
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# Top level modules:
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# uart_tx_top_tb
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# End time: 20:31:23 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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restart
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# Loading work.uart_tx_top_tb
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# Loading work.uart_tx
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# Loading work.ram_uart
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:51 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v
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# -- Compiling module ram_uart
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#
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# Top level modules:
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# ram_uart
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# End time: 20:31:51 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:51 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v
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# -- Compiling module uart_tx
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#
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# Top level modules:
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# uart_tx
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# End time: 20:31:51 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:51 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v
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# -- Compiling module uart_tx_top
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#
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# Top level modules:
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# uart_tx_top
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# End time: 20:31:52 on Jan 03,2019, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:31:52 on Jan 03,2019
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# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v
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# -- Compiling module uart_tx_top_tb
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#
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# Top level modules:
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# uart_tx_top_tb
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# End time: 20:31:52 on Jan 03,2019, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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restart
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# Loading work.uart_tx_top_tb
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# Loading work.uart_tx_top
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# Loading work.uart_tx
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# Loading work.ram_uart
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run -all
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# GetModuleFileName: <20>Ҳ<EFBFBD><D2B2><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ģ<EFBFBD>顣
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#
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#
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# Warning: read_during_write_mode_mixed_ports is assumed as OLD_DATA
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# Time: 0 Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
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# ** Note: $stop : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
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# Time: 2000100 ns Iteration: 0 Instance: /uart_tx_top_tb
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# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
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vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip} {F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 20:32:40 on Jan 03,2019
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/ip" F:/Code/FPGA/study/uart_tx _cpoy/ip/ram_uart.v
|
||
# -- Compiling module ram_uart
|
||
#
|
||
# Top level modules:
|
||
# ram_uart
|
||
# End time: 20:32:40 on Jan 03,2019, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v}
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 20:32:40 on Jan 03,2019
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx.v
|
||
# -- Compiling module uart_tx
|
||
#
|
||
# Top level modules:
|
||
# uart_tx
|
||
# End time: 20:32:40 on Jan 03,2019, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl} {F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v}
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 20:32:41 on Jan 03,2019
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/rtl" F:/Code/FPGA/study/uart_tx _cpoy/rtl/uart_tx_top.v
|
||
# -- Compiling module uart_tx_top
|
||
#
|
||
# Top level modules:
|
||
# uart_tx_top
|
||
# End time: 20:32:41 on Jan 03,2019, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
vlog -vlog01compat -work work {+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench} {F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v}
|
||
# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
|
||
# Start time: 20:32:41 on Jan 03,2019
|
||
# vlog -reportprogress 300 -vlog01compat -work work "+incdir+F:/Code/FPGA/study/uart_tx _cpoy/testbench" F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v
|
||
# -- Compiling module uart_tx_top_tb
|
||
#
|
||
# Top level modules:
|
||
# uart_tx_top_tb
|
||
# End time: 20:32:41 on Jan 03,2019, Elapsed time: 0:00:00
|
||
# Errors: 0, Warnings: 0
|
||
restart
|
||
# Loading work.uart_tx_top_tb
|
||
# Loading work.uart_tx_top
|
||
# Loading work.uart_tx
|
||
# Loading work.ram_uart
|
||
run -all
|
||
# GetModuleFileName: <20>Ҳ<EFBFBD><D2B2><EFBFBD>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ģ<EFBFBD>顣
|
||
#
|
||
#
|
||
# Warning: read_during_write_mode_mixed_ports is assumed as OLD_DATA
|
||
# Time: 0 Instance: uart_tx_top_tb.u0.ram0.altsyncram_component.m_default.altsyncram_inst
|
||
# ** Note: $stop : F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v(37)
|
||
# Time: 6000100 ns Iteration: 0 Instance: /uart_tx_top_tb
|
||
# Break in Module uart_tx_top_tb at F:/Code/FPGA/study/uart_tx _cpoy/testbench/uart_tx_top_tb.v line 37
|
||
# End time: 21:46:51 on Jan 03,2019, Elapsed time: 1:24:14
|
||
# Errors: 3, Warnings: 0
|