31 lines
499 B
Verilog
31 lines
499 B
Verilog
module decoder_138(
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a0,
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a1,
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a2,
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out_n
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);
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input a0;
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input a1;
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input a2;
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output reg [7:0] out_n;
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always @(a0 or a1 or a2)
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begin
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case({a0,a1,a2})
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3'b000:out_n = 8'b1111_1110;
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3'b001:out_n = 8'b1111_1101;
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3'b010:out_n = 8'b1111_1011;
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3'b011:out_n = 8'b1111_0111;
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3'b100:out_n = 8'b1110_1111;
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3'b101:out_n = 8'b1101_1111;
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3'b110:out_n = 8'b1011_1111;
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3'b111:out_n = 8'b0111_1111;
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endcase
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end
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endmodule
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