140 lines
3.0 KiB
Verilog
140 lines
3.0 KiB
Verilog
module AD9226(
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clk,
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rst_n,
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En_Conv,
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DIV_PARAM,
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AD_IN,
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clk_out,
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Conv_Done,
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ADC_State,
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AD_OUT
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);
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input clk;
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input rst_n;
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input En_Conv;
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input [7:0]DIV_PARAM;//分频
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input [11:0] AD_IN;
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output reg clk_out;//时钟输出
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output reg Conv_Done;//转化完成
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output ADC_State;//转换状态
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output reg [11:0] AD_OUT;
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parameter FILTER_PARAM = 3'd5; //除以32 == 右移5位
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parameter CON_CNT = 6'd35;
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reg en;
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reg [7:0] DIV_CNT;
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reg [5:0] con_cnt;
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reg [11:0] AD_MAX,AD_MIN;
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reg [17:0] AD_SUM;
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reg [2:0] adc_clked;
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wire adc_pedge,adc_nedge;
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assign ADC_State = en;
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assign adc_nedge = !adc_clked[1] & adc_clked[2];
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assign adc_pedge = adc_clked[1] & (!adc_clked[2]);
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always @(posedge clk or negedge rst_n)
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if(!rst_n)
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adc_clked <= 3'd0;
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else
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adc_clked <= {adc_clked[1:0],clk_out};
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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con_cnt <= 6'd0;
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else if (Conv_Done)
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con_cnt <= 6'd0;
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else if (adc_pedge)
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con_cnt <= con_cnt + 1'd1;
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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Conv_Done <= 1'b0;
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else if((con_cnt == CON_CNT - 1'b1) && adc_nedge)
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Conv_Done <= 1'b1;
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else
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Conv_Done <= 1'b0;
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//产生使能转换信号
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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en <= 1'b0;
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else if(En_Conv)
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en <= 1'b1;
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else if(Conv_Done)
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en <= 1'b0;
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else
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en <= en;
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//生成SCLK使能时钟计数器
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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DIV_CNT <= 8'd0;
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else if(en)
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begin
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if(DIV_CNT == (DIV_PARAM - 1'b1))
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DIV_CNT <= 8'd0;
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else
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DIV_CNT <= DIV_CNT + 1'b1;
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end
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else
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DIV_CNT <= 8'd0;
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//生成SCLK使能时钟
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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clk_out <= 1'b0;
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else if(en && (DIV_CNT == (DIV_PARAM - 1'b1)))
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clk_out <= (~clk_out);
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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AD_MAX <= 12'd0;
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else if(Conv_Done || en == 1'b0)
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AD_MAX <= 12'd0;
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else if(adc_pedge)begin//转换完成，转换计数为奇数，判断当前值是否大于已存最大值
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if(AD_IN > AD_MAX)
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AD_MAX <= AD_IN;
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end
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//记录采样的最小值
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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AD_MIN <= 12'd0;
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else if(Conv_Done || en == 1'b0)
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AD_MIN <= 12'd4095;
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else if(adc_pedge)begin//转换完成，转换计数为奇数，判断当前值是否小于已存最小值
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if(AD_IN < AD_MIN)
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AD_MIN<= AD_IN;
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end
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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AD_SUM <= 18'd0;
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else if(Conv_Done || en == 1'b0)
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AD_SUM <= 18'd0;
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else if(adc_pedge)//转换完成，转换计数为偶数，将转换结果累加到Y临时寄存器
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AD_SUM <= AD_SUM + AD_IN;
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always@(posedge clk or negedge rst_n)
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if(!rst_n)
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AD_OUT <= 12'd0;
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else if((con_cnt == CON_CNT - 1'b1) && adc_nedge)
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AD_OUT <= (AD_SUM - AD_MIN - AD_MAX) >> FILTER_PARAM;
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endmodule
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