81 lines
3.5 KiB
Plaintext
81 lines
3.5 KiB
Plaintext
--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=1024 LPM_SHOWAHEAD="OFF" lpm_width=12 lpm_widthu=10 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" clock data empty full q rreq sclr usedw wreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO"
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--VERSION_BEGIN 18.0 cbx_altdpram 2018:04:24:18:04:18:SJ cbx_altera_counter 2018:04:24:18:04:18:SJ cbx_altera_syncram 2018:04:24:18:04:18:SJ cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_fifo_common 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_scfifo 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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FUNCTION a_fefifo_jaf (aclr, clock, rreq, sclr, wreq)
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RETURNS ( empty, full, usedw_out[9..0]);
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FUNCTION altsyncram_osm1 (address_a[9..0], address_b[9..0], clock0, clock1, clocken1, data_a[11..0], wren_a)
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RETURNS ( q_b[11..0]);
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FUNCTION cntr_cpb (aclr, clock, cnt_en, sclr)
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RETURNS ( q[9..0]);
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--synthesis_resources = lut 30 M9K 2 reg 32
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SUBDESIGN a_dpfifo_i041
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(
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clock : input;
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data[11..0] : input;
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empty : output;
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full : output;
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q[11..0] : output;
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rreq : input;
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sclr : input;
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usedw[9..0] : output;
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wreq : input;
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)
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VARIABLE
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fifo_state : a_fefifo_jaf;
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FIFOram : altsyncram_osm1;
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rd_ptr_count : cntr_cpb;
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wr_ptr : cntr_cpb;
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aclr : NODE;
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rd_ptr[9..0] : WIRE;
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valid_rreq : WIRE;
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valid_wreq : WIRE;
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BEGIN
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fifo_state.aclr = aclr;
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fifo_state.clock = clock;
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fifo_state.rreq = rreq;
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fifo_state.sclr = sclr;
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fifo_state.wreq = wreq;
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FIFOram.address_a[] = wr_ptr.q[];
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FIFOram.address_b[] = ((! sclr) & rd_ptr[]);
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FIFOram.clock0 = clock;
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FIFOram.clock1 = clock;
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FIFOram.clocken1 = (valid_rreq # sclr);
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FIFOram.data_a[] = data[];
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FIFOram.wren_a = valid_wreq;
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rd_ptr_count.aclr = aclr;
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rd_ptr_count.clock = clock;
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rd_ptr_count.cnt_en = valid_rreq;
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rd_ptr_count.sclr = sclr;
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wr_ptr.aclr = aclr;
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wr_ptr.clock = clock;
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wr_ptr.cnt_en = valid_wreq;
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wr_ptr.sclr = sclr;
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aclr = GND;
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empty = fifo_state.empty;
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full = fifo_state.full;
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q[] = FIFOram.q_b[];
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rd_ptr[] = rd_ptr_count.q[];
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usedw[] = fifo_state.usedw_out[];
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valid_rreq = (rreq & (! fifo_state.empty));
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valid_wreq = (wreq & (! fifo_state.full));
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END;
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--VALID FILE
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