14 lines
5.6 KiB
Plaintext
14 lines
5.6 KiB
Plaintext
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1540205985266 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1540205985282 ""} { "Info" "IQEXE_START_BANNER_TIME" "Mon Oct 22 18:59:45 2018 " "Processing started: Mon Oct 22 18:59:45 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1540205985282 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1540205985282 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off adc_uart -c adc_uart " "Command: quartus_eda --read_settings_files=off --write_settings_files=off adc_uart -c adc_uart" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1540205985283 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1540205985842 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_8_1200mv_85c_slow.vo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_8_1200mv_85c_slow.vo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986021 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_8_1200mv_0c_slow.vo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_8_1200mv_0c_slow.vo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986067 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_min_1200mv_0c_fast.vo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_min_1200mv_0c_fast.vo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986126 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart.vo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart.vo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986183 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_8_1200mv_85c_v_slow.sdo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_8_1200mv_85c_v_slow.sdo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986219 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_8_1200mv_0c_v_slow.sdo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_8_1200mv_0c_v_slow.sdo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986266 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_min_1200mv_0c_v_fast.sdo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_min_1200mv_0c_v_fast.sdo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986312 ""}
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{ "Info" "IWSC_DONE_HDL_GENERATION" "adc_uart_v.sdo F:/Code/FPGA/study/adc_uart/simulation/modelsim/ simulation " "Generated file adc_uart_v.sdo in folder \"F:/Code/FPGA/study/adc_uart/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1540205986360 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4664 " "Peak virtual memory: 4664 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1540205986433 ""} { "Info" "IQEXE_END_BANNER_TIME" "Mon Oct 22 18:59:46 2018 " "Processing ended: Mon Oct 22 18:59:46 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1540205986433 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1540205986433 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1540205986433 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1540205986433 ""}
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