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study/other/adc_uart/db/cntr_op7.tdf
2020-06-09 15:48:03 +08:00

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--lpm_counter DEVICE_FAMILY="Cyclone IV E" lpm_width=10 aclr clock cnt_en q sclr updown
--VERSION_BEGIN 18.0 cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ VERSION_END
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
-- Your use of Intel Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Intel Program License
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
-- the Intel FPGA IP License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for
-- the sole purpose of programming logic devices manufactured by
-- Intel and sold by Intel or its authorized distributors. Please
-- refer to the applicable agreement for further details.
FUNCTION cycloneive_lcell_comb (cin, dataa, datab, datac, datad)
WITH ( DONT_TOUCH, LUT_MASK, SUM_LUTC_INPUT)
RETURNS ( combout, cout);
--synthesis_resources = lut 10 reg 10
SUBDESIGN cntr_op7
(
aclr : input;
clock : input;
cnt_en : input;
q[9..0] : output;
sclr : input;
updown : input;
)
VARIABLE
counter_comb_bita0 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita1 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita2 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita3 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita4 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita5 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita6 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita7 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita8 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_comb_bita9 : cycloneive_lcell_comb
WITH (
LUT_MASK = "5A90",
SUM_LUTC_INPUT = "cin"
);
counter_reg_bit[9..0] : dffeas;
aclr_actual : WIRE;
clk_en : NODE;
data[9..0] : NODE;
external_cin : WIRE;
s_val[9..0] : WIRE;
safe_q[9..0] : WIRE;
sload : NODE;
sset : NODE;
updown_dir : WIRE;
BEGIN
counter_comb_bita[9..0].cin = ( counter_comb_bita[8..0].cout, external_cin);
counter_comb_bita[9..0].dataa = ( counter_reg_bit[9..0].q);
counter_comb_bita[9..0].datab = ( updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir, updown_dir);
counter_comb_bita[9..0].datad = ( B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1", B"1");
counter_reg_bit[].asdata = ((! sclr) & ((sset & s_val[]) # ((! sset) & data[])));
counter_reg_bit[].clk = clock;
counter_reg_bit[].clrn = (! aclr_actual);
counter_reg_bit[].d = ( counter_comb_bita[9..0].combout);
counter_reg_bit[].ena = (clk_en & (((sclr # sset) # sload) # cnt_en));
counter_reg_bit[].sload = ((sclr # sset) # sload);
aclr_actual = aclr;
clk_en = VCC;
data[] = GND;
external_cin = B"1";
q[] = safe_q[];
s_val[] = B"1111111111";
safe_q[] = counter_reg_bit[].q;
sload = GND;
sset = GND;
updown_dir = updown;
END;
--VALID FILE