52 lines
2.6 KiB
Plaintext
52 lines
2.6 KiB
Plaintext
--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone IV E" LPM_NUMWORDS=1024 LPM_SHOWAHEAD="OFF" LPM_WIDTH=12 LPM_WIDTHU=10 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="ON" UNDERFLOW_CHECKING="ON" USE_EAB="ON" clock data empty full q rdreq usedw wrreq CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 CYCLONEII_M4K_COMPATIBILITY="ON" INTENDED_DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO"
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--VERSION_BEGIN 18.0 cbx_altdpram 2018:04:24:18:04:18:SJ cbx_altera_counter 2018:04:24:18:04:18:SJ cbx_altera_syncram 2018:04:24:18:04:18:SJ cbx_altera_syncram_nd_impl 2018:04:24:18:04:18:SJ cbx_altsyncram 2018:04:24:18:04:18:SJ cbx_cycloneii 2018:04:24:18:04:18:SJ cbx_fifo_common 2018:04:24:18:04:18:SJ cbx_lpm_add_sub 2018:04:24:18:04:18:SJ cbx_lpm_compare 2018:04:24:18:04:18:SJ cbx_lpm_counter 2018:04:24:18:04:18:SJ cbx_lpm_decode 2018:04:24:18:04:18:SJ cbx_lpm_mux 2018:04:24:18:04:18:SJ cbx_mgl 2018:04:24:18:08:49:SJ cbx_nadder 2018:04:24:18:04:18:SJ cbx_scfifo 2018:04:24:18:04:18:SJ cbx_stratix 2018:04:24:18:04:18:SJ cbx_stratixii 2018:04:24:18:04:18:SJ cbx_stratixiii 2018:04:24:18:04:18:SJ cbx_stratixv 2018:04:24:18:04:18:SJ cbx_util_mgl 2018:04:24:18:04:18:SJ VERSION_END
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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FUNCTION a_dpfifo_i041 (clock, data[11..0], rreq, sclr, wreq)
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RETURNS ( empty, full, q[11..0], usedw[9..0]);
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--synthesis_resources = lut 30 M9K 2 reg 32
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SUBDESIGN scfifo_bq31
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(
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clock : input;
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data[11..0] : input;
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empty : output;
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full : output;
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q[11..0] : output;
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rdreq : input;
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usedw[9..0] : output;
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wrreq : input;
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)
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VARIABLE
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dpfifo : a_dpfifo_i041;
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sclr : NODE;
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BEGIN
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dpfifo.clock = clock;
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dpfifo.data[] = data[];
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dpfifo.rreq = rdreq;
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dpfifo.sclr = sclr;
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dpfifo.wreq = wrreq;
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empty = dpfifo.empty;
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full = dpfifo.full;
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q[] = dpfifo.q[];
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sclr = GND;
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usedw[] = dpfifo.usedw[];
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END;
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--VALID FILE
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