77 lines
3.6 KiB
Plaintext
77 lines
3.6 KiB
Plaintext
# Reading D:/intelFPGA/18.0/modelsim_ase/tcl/vsim/pref.tcl
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# do ip_nco_run_msim_rtl_verilog.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap work rtl_work
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# Copying D:/intelFPGA/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
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# Modifying modelsim.ini
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#
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# vlib nco_ip
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# vmap nco_ip nco_ip
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap nco_ip nco_ip
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# Modifying modelsim.ini
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# vlog -vlog01compat -work nco_ip +incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis {F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/nco_ip.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:32:36 on Oct 27,2018
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# vlog -reportprogress 300 -vlog01compat -work nco_ip "+incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis" F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/nco_ip.v
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# -- Compiling module nco_ip
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#
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# Top level modules:
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# nco_ip
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# End time: 20:32:36 on Oct 27,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vlog -vlog01compat -work nco_ip +incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules {F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules/nco_ip_nco_ii_0.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:32:36 on Oct 27,2018
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# vlog -reportprogress 300 -vlog01compat -work nco_ip "+incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules" F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules/nco_ip_nco_ii_0.v
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# -- Compiling module nco_ip_nco_ii_0
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#
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# Top level modules:
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# nco_ip_nco_ii_0
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# End time: 20:32:36 on Oct 27,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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do F:/Code/FPGA/study/ip_nco/simulation/modelsim/ip_nco_run_msim_rtl_verilog.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap work rtl_work
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# Modifying modelsim.ini
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#
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# vlib nco_ip
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# ** Warning: (vlib-34) Library already exists at "nco_ip".
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# vmap nco_ip nco_ip
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap nco_ip nco_ip
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# Modifying modelsim.ini
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# vlog -vlog01compat -work nco_ip +incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis {F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/nco_ip.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:33:17 on Oct 27,2018
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# vlog -reportprogress 300 -vlog01compat -work nco_ip "+incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis" F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/nco_ip.v
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# -- Compiling module nco_ip
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#
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# Top level modules:
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# nco_ip
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# End time: 20:33:17 on Oct 27,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vlog -vlog01compat -work nco_ip +incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules {F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules/nco_ip_nco_ii_0.v}
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# Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:33:17 on Oct 27,2018
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# vlog -reportprogress 300 -vlog01compat -work nco_ip "+incdir+F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules" F:/Code/FPGA/study/ip_nco/ip/nco_ip/synthesis/submodules/nco_ip_nco_ii_0.v
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# -- Compiling module nco_ip_nco_ii_0
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#
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# Top level modules:
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# nco_ip_nco_ii_0
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# End time: 20:33:18 on Oct 27,2018, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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#
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# ERROR: No extended dataflow license exists
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