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study/other/nios_usart/my_cpu/my_cpu_generation.rpt
sansi 7706b9a86c first commit
2020-06-09 15:48:03 +08:00

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Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate F:\Code\FPGA\study\nios_usart\my_cpu.qsys --block-symbol-file --output-directory=F:\Code\FPGA\study\nios_usart\my_cpu --family="Cyclone IV E" --part=EP4CE10F17C8
Progress: Loading nios_usart/my_cpu.qsys
Progress: Reading input file
Progress: Adding P0 [altera_avalon_pio 18.0]
Progress: Parameterizing module P0
Progress: Adding clk_0 [clock_source 18.0]
Progress: Parameterizing module clk_0
Progress: Adding cpu_id [altera_avalon_sysid_qsys 18.0]
Progress: Parameterizing module cpu_id
Progress: Adding nios2_cpu [altera_nios2_gen2 18.0]
Progress: Parameterizing module nios2_cpu
Progress: Adding ram [altera_avalon_onchip_memory2 18.0]
Progress: Parameterizing module ram
Progress: Adding rom [altera_avalon_onchip_memory2 18.0]
Progress: Parameterizing module rom
Progress: Adding uart_0 [altera_avalon_uart 18.0]
Progress: Parameterizing module uart_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_cpu.P0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: my_cpu.cpu_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: my_cpu.cpu_id: Time stamp will be automatically updated when this component is generated.
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info:
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate F:\Code\FPGA\study\nios_usart\my_cpu.qsys --synthesis=VERILOG --output-directory=F:\Code\FPGA\study\nios_usart\my_cpu\synthesis --family="Cyclone IV E" --part=EP4CE10F17C8
Progress: Loading nios_usart/my_cpu.qsys
Progress: Reading input file
Progress: Adding P0 [altera_avalon_pio 18.0]
Progress: Parameterizing module P0
Progress: Adding clk_0 [clock_source 18.0]
Progress: Parameterizing module clk_0
Progress: Adding cpu_id [altera_avalon_sysid_qsys 18.0]
Progress: Parameterizing module cpu_id
Progress: Adding nios2_cpu [altera_nios2_gen2 18.0]
Progress: Parameterizing module nios2_cpu
Progress: Adding ram [altera_avalon_onchip_memory2 18.0]
Progress: Parameterizing module ram
Progress: Adding rom [altera_avalon_onchip_memory2 18.0]
Progress: Parameterizing module rom
Progress: Adding uart_0 [altera_avalon_uart 18.0]
Progress: Parameterizing module uart_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Info: my_cpu.P0: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
Info: my_cpu.cpu_id: System ID is not assigned automatically. Edit the System ID parameter to provide a unique ID
Info: my_cpu.cpu_id: Time stamp will be automatically updated when this component is generated.
Info: my_cpu: Generating my_cpu "my_cpu" for QUARTUS_SYNTH
Info: P0: Starting RTL generation for module 'my_cpu_P0'
Info: P0: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=my_cpu_P0 --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0028_P0_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0028_P0_gen//my_cpu_P0_component_configuration.pl --do_build_sim=0 ]
Info: P0: Done RTL generation for module 'my_cpu_P0'
Info: P0: "my_cpu" instantiated altera_avalon_pio "P0"
Info: cpu_id: "my_cpu" instantiated altera_avalon_sysid_qsys "cpu_id"
Info: nios2_cpu: "my_cpu" instantiated altera_nios2_gen2 "nios2_cpu"
Info: ram: Starting RTL generation for module 'my_cpu_ram'
Info: ram: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=my_cpu_ram --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0030_ram_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0030_ram_gen//my_cpu_ram_component_configuration.pl --do_build_sim=0 ]
Info: ram: Done RTL generation for module 'my_cpu_ram'
Info: ram: "my_cpu" instantiated altera_avalon_onchip_memory2 "ram"
Info: rom: Starting RTL generation for module 'my_cpu_rom'
Info: rom: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2 -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_onchip_memory2/generate_rtl.pl --name=my_cpu_rom --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0031_rom_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0031_rom_gen//my_cpu_rom_component_configuration.pl --do_build_sim=0 ]
Info: rom: Done RTL generation for module 'my_cpu_rom'
Info: rom: "my_cpu" instantiated altera_avalon_onchip_memory2 "rom"
Info: uart_0: Starting RTL generation for module 'my_cpu_uart_0'
Info: uart_0: Generation command is [exec D:/intelfpga/18.0/quartus/bin64/perl/bin/perl.exe -I D:/intelfpga/18.0/quartus/bin64/perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/common -I D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart -- D:/intelfpga/18.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_uart/generate_rtl.pl --name=my_cpu_uart_0 --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0032_uart_0_gen/ --quartus_dir=D:/intelfpga/18.0/quartus --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0032_uart_0_gen//my_cpu_uart_0_component_configuration.pl --do_build_sim=0 ]
Info: uart_0: Done RTL generation for module 'my_cpu_uart_0'
Info: uart_0: "my_cpu" instantiated altera_avalon_uart "uart_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_003: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_004: Inserting error_adapter: error_adapter_0
Info: avalon_st_adapter_005: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "my_cpu" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: irq_mapper: "my_cpu" instantiated altera_irq_mapper "irq_mapper"
Info: rst_controller: "my_cpu" instantiated altera_reset_controller "rst_controller"
Info: cpu: Starting RTL generation for module 'my_cpu_nios2_cpu_cpu'
Info: cpu: Generation command is [exec D:/intelFPGA/18.0/quartus/bin64//eperlcmd.exe -I D:/intelFPGA/18.0/quartus/bin64//perl/lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin/europa -I D:/intelfpga/18.0/quartus/sopc_builder/bin/perl_lib -I D:/intelfpga/18.0/quartus/sopc_builder/bin -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/cpu_lib -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/nios_lib -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -I D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2 -- D:/intelfpga/18.0/quartus/../ip/altera/nios2_ip/altera_nios2_gen2/generate_rtl.epl --name=my_cpu_nios2_cpu_cpu --dir=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0035_cpu_gen/ --quartus_bindir=D:/intelFPGA/18.0/quartus/bin64/ --verilog --config=C:/Users/sansi/AppData/Local/Temp/alt7847_3082908581063472218.dir/0035_cpu_gen//my_cpu_nios2_cpu_cpu_processor_configuration.pl --do_build_sim=0 ]
Info: cpu: # 2018.11.12 19:36:33 (*) Starting Nios II generation
Info: cpu: # 2018.11.12 19:36:33 (*) Checking for plaintext license.
Info: cpu: # 2018.11.12 19:36:34 (*) Plaintext license not found.
Info: cpu: # 2018.11.12 19:36:34 (*) Checking for encrypted license (non-evaluation).
Info: cpu: # 2018.11.12 19:36:35 (*) Encrypted license found. SOF will not be time-limited.
Info: cpu: # 2018.11.12 19:36:35 (*) Elaborating CPU configuration settings
Info: cpu: # 2018.11.12 19:36:35 (*) Creating all objects for CPU
Info: cpu: # 2018.11.12 19:36:35 (*) Testbench
Info: cpu: # 2018.11.12 19:36:35 (*) Instruction decoding
Info: cpu: # 2018.11.12 19:36:35 (*) Instruction fields
Info: cpu: # 2018.11.12 19:36:36 (*) Instruction decodes
Info: cpu: # 2018.11.12 19:36:36 (*) Signals for RTL simulation waveforms
Info: cpu: # 2018.11.12 19:36:36 (*) Instruction controls
Info: cpu: # 2018.11.12 19:36:36 (*) Pipeline frontend
Info: cpu: # 2018.11.12 19:36:36 (*) Pipeline backend
Info: cpu: # 2018.11.12 19:36:39 (*) Generating RTL from CPU objects
Info: cpu: # 2018.11.12 19:36:41 (*) Creating encrypted RTL
Info: cpu: # 2018.11.12 19:36:42 (*) Done Nios II generation
Info: cpu: Done RTL generation for module 'my_cpu_nios2_cpu_cpu'
Info: cpu: "nios2_cpu" instantiated altera_nios2_gen2_unit "cpu"
Info: nios2_cpu_data_master_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "nios2_cpu_data_master_translator"
Info: cpu_id_control_slave_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "cpu_id_control_slave_translator"
Info: nios2_cpu_data_master_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "nios2_cpu_data_master_agent"
Info: cpu_id_control_slave_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "cpu_id_control_slave_agent"
Info: cpu_id_control_slave_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "cpu_id_control_slave_agent_rsp_fifo"
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: router_002: "mm_interconnect_0" instantiated altera_merlin_router "router_002"
Info: router_003: "mm_interconnect_0" instantiated altera_merlin_router "router_003"
Info: nios2_cpu_data_master_limiter: "mm_interconnect_0" instantiated altera_merlin_traffic_limiter "nios2_cpu_data_master_limiter"
Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_avalon_sc_fifo.v
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux_001"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: cmd_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux_001"
Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux"
Info: rsp_demux_001: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "rsp_demux_001"
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux_001: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux_001"
Info: Reusing file F:/Code/FPGA/study/nios_usart/my_cpu/synthesis/submodules/altera_merlin_arbitrator.sv
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: my_cpu: Done "my_cpu" with 31 modules, 52 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis
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