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sansi 7706b9a86c first commit

2020-06-09 15:48:03 +08:00

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rtl_work

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modelsim.ini

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msim_transcript

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uart_tx_8_1200mv_0c_slow.vo

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uart_tx_8_1200mv_0c_v_slow.sdo

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uart_tx_8_1200mv_85c_slow.vo

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uart_tx_8_1200mv_85c_v_slow.sdo

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uart_tx_min_1200mv_0c_fast.vo

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uart_tx_min_1200mv_0c_v_fast.sdo

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uart_tx_modelsim.xrf

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uart_tx_run_msim_rtl_verilog.do

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uart_tx_run_msim_rtl_verilog.do.bak

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uart_tx_run_msim_rtl_verilog.do.bak1

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uart_tx_run_msim_rtl_verilog.do.bak2

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uart_tx_run_msim_rtl_verilog.do.bak3

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uart_tx_run_msim_rtl_verilog.do.bak4

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uart_tx_run_msim_rtl_verilog.do.bak5

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uart_tx_run_msim_rtl_verilog.do.bak6

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uart_tx_run_msim_rtl_verilog.do.bak7

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uart_tx_run_msim_rtl_verilog.do.bak8

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uart_tx_run_msim_rtl_verilog.do.bak9

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uart_tx_run_msim_rtl_verilog.do.bak10

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uart_tx_run_msim_rtl_verilog.do.bak11

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uart_tx_v.sdo

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uart_tx.sft

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uart_tx.vo

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uart_tx.vt

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vsim.wlf

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