47 lines
497 B
Coq
47 lines
497 B
Coq
`timescale 1ns/1ns
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`define clk_period 20
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module uart_tx_tb;
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reg [1:0] baud_set;
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reg clk;
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reg [7:0] data;
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reg en;
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reg rst_n;
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wire tx;
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wire tx_done;
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uart_tx i1 (
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.baud_set(baud_set),
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.clk(clk),
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.data(data),
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.en(en),
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.rst_n(rst_n),
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.tx(tx),
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.tx_done(tx_done)
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);
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//generater clock
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initial clk = 1;
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always #(`clk_period/2)clk = ~clk;
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integer i;
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initial begin
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$stop;
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end
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endmodule
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