From 05e30be3ee059c2ff3d315ac0a97823eb04d93bf Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 9 Oct 2019 12:55:16 +0200
Subject: [PATCH] sim: add Host/Device USB3 PIPE

---
 sim.py | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/sim.py b/sim.py
index f571f03..0e637be 100755
--- a/sim.py
+++ b/sim.py
@@ -11,6 +11,10 @@ from litex.build.sim.config import SimConfig
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 
+
+from usb3_pipe import USB3SerDesModel
+from usb3_pipe import USB3PIPE
+
 # IOs ----------------------------------------------------------------------------------------------
 
 class SimPins(Pins):
@@ -39,9 +43,22 @@ class Platform(SimPlatform):
 class USB3PIPESim(SoCMini):
     def __init__(self):
         platform = Platform()
-        sys_clk_freq = int(1e6)
+        sys_clk_freq = int(133e6)
         SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
 
+        # USB3 Host
+        host_usb3_serdes = USB3SerDesModel()
+        host_usb3_pipe   = USB3PIPE(serdes=host_usb3_serdes, sys_clk_freq=sys_clk_freq)
+        self.submodules += host_usb3_serdes, host_usb3_pipe
+
+        # USB3 Device
+        dev_usb3_serdes = USB3SerDesModel()
+        dev_usb3_pipe   = USB3PIPE(serdes=dev_usb3_serdes, sys_clk_freq=sys_clk_freq)
+        self.submodules += dev_usb3_serdes, dev_usb3_pipe
+
+        # Connect Host <--> Device
+        self.comb += host_usb3_serdes.connect(dev_usb3_serdes)
+
 # Build --------------------------------------------------------------------------------------------
 
 def main():