FPGA/usb3_pipe
1
0
Fork 0
mirror of https://github.com/enjoy-digital/usb3_pipe.git synced 2025-01-04 10:18:41 +08:00
Code Issues Projects Releases Wiki Activity

sim: add Host/Device USB3 PIPE

Browse Source
This commit is contained in:
Florent Kermarrec 2019-10-09 12:55:16 +02:00
parent c77296f798
commit 05e30be3ee
1 changed files with 18 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
sim.py
View File

@ -11,6 +11,10 @@ from litex.build.sim.config import SimConfig
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *
from usb3_pipe import USB3SerDesModel
from usb3_pipe import USB3PIPE
# IOs ---------------------------------------------------------------------------------------------- # IOs ----------------------------------------------------------------------------------------------
class SimPins(Pins): class SimPins(Pins):
@ -39,9 +43,22 @@ class Platform(SimPlatform):
class USB3PIPESim(SoCMini): class USB3PIPESim(SoCMini):
def __init__(self): def __init__(self):
platform = Platform() platform = Platform()
sys_clk_freq = int(1e6) sys_clk_freq = int(133e6)
SoCMini.__init__(self, platform, clk_freq=sys_clk_freq) SoCMini.__init__(self, platform, clk_freq=sys_clk_freq)
# USB3 Host
host_usb3_serdes = USB3SerDesModel()
host_usb3_pipe = USB3PIPE(serdes=host_usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += host_usb3_serdes, host_usb3_pipe
# USB3 Device
dev_usb3_serdes = USB3SerDesModel()
dev_usb3_pipe = USB3PIPE(serdes=dev_usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += dev_usb3_serdes, dev_usb3_pipe
# Connect Host <--> Device
self.comb += host_usb3_serdes.connect(dev_usb3_serdes)
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():