FPGA/usb3_pipe
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versa_ecp5: fix ispclk control, use channel 0 (pcie), add clocks debug leds

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This commit is contained in:
Florent Kermarrec 2019-10-18 14:49:11 +02:00
parent a5f94f1f0c
commit 0cb086d924
2 changed files with 21 additions and 6 deletions
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1
usb3_pipe/serdes.py
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@ -471,7 +471,6 @@ class ECP5USB3SerDes(Module):
if isinstance(refclk_pads, (Signal, ClockSignal)): if isinstance(refclk_pads, (Signal, ClockSignal)):
refclk = refclk_pads refclk = refclk_pads
else: else:
refclk = Signal()
refclk = Signal() refclk = Signal()
self.specials.extref0 = Instance("EXTREFB", self.specials.extref0 = Instance("EXTREFB",
i_REFCLKP=refclk_pads.p, i_REFCLKP=refclk_pads.p,

26
versa_ecp5.py
View File

@ -81,13 +81,16 @@ class USB3SoC(SoCMini):
self.add_wb_master(self.bridge.wishbone) self.add_wb_master(self.bridge.wishbone)
# USB3 SerDes ------------------------------------------------------------------------------ # USB3 SerDes ------------------------------------------------------------------------------
self.comb += platform.request("refclk_en").eq(1)
self.comb += platform.request("refclk_rst_n").eq(1)
usb3_serdes = ECP5USB3SerDes(platform, usb3_serdes = ECP5USB3SerDes(platform,
sys_clk = self.crg.cd_sys.clk, sys_clk = self.crg.cd_sys.clk,
sys_clk_freq = sys_clk_freq, sys_clk_freq = sys_clk_freq,
refclk_pads = platform.request("refclk", 1), refclk_pads = platform.request("refclk", 1),
refclk_freq = 156.25e6, refclk_freq = 156.25e6,
tx_pads = platform.request(connector + "_tx"), tx_pads = platform.request(connector + "_tx"),
rx_pads = platform.request(connector + "_rx")) rx_pads = platform.request(connector + "_rx"),
channel = 0)
self.submodules += usb3_serdes self.submodules += usb3_serdes
# USB3 PIPE -------------------------------------------------------------------------------- # USB3 PIPE --------------------------------------------------------------------------------
@ -96,10 +99,6 @@ class USB3SoC(SoCMini):
self.comb += usb3_pipe.sink.valid.eq(1) self.comb += usb3_pipe.sink.valid.eq(1)
self.comb += usb3_pipe.source.ready.eq(1) self.comb += usb3_pipe.source.ready.eq(1)
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready)
# Analyzer --------------------------------------------------------------------------------- # Analyzer ---------------------------------------------------------------------------------
if with_analyzer: if with_analyzer:
analyzer_signals = [ analyzer_signals = [
@ -136,6 +135,23 @@ class USB3SoC(SoCMini):
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv") self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer") self.add_csr("analyzer")
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_pipe.ready)
sys_counter = Signal(32)
self.sync.sys += sys_counter.eq(sys_counter + 1)
self.comb += platform.request("user_led", 4).eq(sys_counter[26])
rx_counter = Signal(32)
self.sync.rx += rx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 5).eq(rx_counter[26])
tx_counter = Signal(32)
self.sync.tx += tx_counter.eq(rx_counter + 1)
self.comb += platform.request("user_led", 6).eq(tx_counter[26])
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------
def main(): def main():