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training: add ts1_inv_checker and use it to detect rx polarity

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This commit is contained in:
Florent Kermarrec 2019-12-04 18:00:08 +01:00
parent c071f56abd
commit 22fc42a9b9
4 changed files with 26 additions and 16 deletions
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3
sim.py
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@ -142,6 +142,7 @@ class USB3PIPESim(SoCMini):
host_usb3_core = USB3Core(platform)
self.submodules.host_usb3_core = host_usb3_core
self.comb += [
host_usb3_serdes.tx_polarity.eq(1), # Inverse TX polarity to test RX auto-polarity
host_usb3_pipe.source.connect(host_usb3_core.sink),
host_usb3_core.source.connect(host_usb3_pipe.sink),
host_usb3_core.reset.eq(~host_usb3_pipe.ready),
@ -159,13 +160,13 @@ class USB3PIPESim(SoCMini):
dev_usb3_core = USB3Core(platform)
self.submodules.dev_usb3_core = dev_usb3_core
self.comb += [
dev_usb3_serdes.tx_polarity.eq(1), # Inverse TX polarity to test RX auto-polarity
dev_usb3_pipe.source.connect(dev_usb3_core.sink),
dev_usb3_core.source.connect(dev_usb3_pipe.sink),
dev_usb3_core.reset.eq(~dev_usb3_pipe.ready),
]
self.add_csr("dev_usb3_core")
# Connect Host <--> Device
self.comb += host_usb3_serdes.connect(dev_usb3_serdes)

5
usb3_pipe/common.py
View File

@ -68,6 +68,11 @@ TS1 = OrderedSet("TS1",
[D( 0, 0), LinkConfig(reset=0, loopback=0, scrambling=1)] +
[D(10, 2) for i in range(10)])
TS1_INV = OrderedSet("TS1",
[COM for i in range(4)] +
[D( 0, 0), LinkConfig(reset=0, loopback=0, scrambling=1)] +
[D(21, 5) for i in range(10)])
TS2 = OrderedSet("TS2",
[COM for i in range(4)] +
[D( 0, 0), LinkConfig(reset=0, loopback=0, scrambling=1)] +

4
usb3_pipe/ltssm.py
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@ -242,13 +242,13 @@ class PollingFSM(Module):
If(_12_ms_timer.done,
NextState("Polling.ExitToRxDetect")
),
# Go to Configuration if at least 8 consecutive TS1 or TS2 seen (8 ensured by ts_unit)
# Go to Configuration if at least 8 consecutive TS1 or TS1_INV seen (8 ensured by ts_unit)
If(ts_unit.rx_ts1,
NextValue(serdes.rx_polarity, 0),
_12_ms_timer.wait.eq(0),
NextState("Polling.Configuration")
),
If(ts_unit.rx_ts2,
If(ts_unit.rx_ts1_inv,
NextValue(serdes.rx_polarity, 1),
_12_ms_timer.wait.eq(0),
NextState("Polling.Configuration")

30
usb3_pipe/training.py
View File

@ -5,7 +5,7 @@ from migen import *
from litex.soc.interconnect import stream
from usb3_pipe.common import TSEQ, TS1, TS2
from usb3_pipe.common import TSEQ, TS1, TS1_INV, TS2
# Training Sequence Checker ------------------------------------------------------------------------
@ -189,26 +189,30 @@ class TSGenerator(Module):
class TSUnit(Module):
def __init__(self, serdes):
self.rx_enable = Signal() # i
self.rx_ts1 = Signal() # o
self.rx_ts2 = Signal() # o
self.rx_enable = Signal() # i
self.rx_ts1 = Signal() # o
self.rx_ts1_inv = Signal() # o
self.rx_ts2 = Signal() # o
self.tx_enable = Signal() # i
self.tx_tseq = Signal() # i
self.tx_ts1 = Signal() # i
self.tx_ts2 = Signal() # i
self.tx_done = Signal() # o
self.tx_enable = Signal() # i
self.tx_tseq = Signal() # i
self.tx_ts1 = Signal() # i
self.tx_ts2 = Signal() # i
self.tx_done = Signal() # o
# # #
# Ordered Set Checkers ---------------------------------------------------------------------
self.submodules.ts1_checker = ts1_checker = TSChecker(ordered_set=TS1, n_ordered_sets=8)
self.submodules.ts2_checker = ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.submodules.ts1_checker = ts1_checker = TSChecker(ordered_set=TS1, n_ordered_sets=8)
self.submodules.ts1_inv_checker = ts1_inv_checker = TSChecker(ordered_set=TS1_INV, n_ordered_sets=8)
self.submodules.ts2_checker = ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.comb += [
serdes.source.connect(ts1_checker.sink, omit={"ready"}),
serdes.source.connect(ts2_checker.sink, omit={"ready"}),
serdes.source.connect(ts1_checker.sink, omit={"ready"}),
serdes.source.connect(ts1_inv_checker.sink, omit={"ready"}),
serdes.source.connect(ts2_checker.sink, omit={"ready"}),
If(self.rx_enable, serdes.source.ready.eq(1)),
self.rx_ts1.eq(ts1_checker.detected),
self.rx_ts1_inv.eq(ts1_inv_checker.detected),
self.rx_ts2.eq(ts2_checker.detected),
]