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control serdes.rx_align, use default value of 1 on enable controls

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This commit is contained in:
Florent Kermarrec 2019-10-08 10:53:52 +02:00
parent 6ebe23f17b
commit 362fe4f444
3 changed files with 20 additions and 11 deletions
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7
usb3_pipe/ltssm.py
View File

@ -163,7 +163,7 @@ class RXDetectFSM(FSM):
@ResetInserter()
class PollingFSM(FSM):
""" Polling Finite State Machine (section 7.5.4)"""
def __init__(self, lfps_unit, ts_unit):
def __init__(self, serdes, lfps_unit, ts_unit):
self.exit_to_compliance_mode = Signal()
self.exit_to_rx_detect = Signal()
self.exit_to_ss_disabled = Signal()
@ -179,6 +179,7 @@ class PollingFSM(FSM):
# LFPS State -------------------------------------------------------------------------------
self.act("LFPS",
serdes.rx_align.eq(1),
lfps_unit.tx_polling.eq(1),
NextState("RX-EQ"), # LFPS handshake.
#self.exit_to_compliance_mode.eq(1), # First LFPS timeout.
@ -189,6 +190,7 @@ class PollingFSM(FSM):
# RxEQ State -------------------------------------------------------------------------------
self.act("RX-EQ",
serdes.rx_align.eq(1),
If(ts_unit.rx_tseq,
NextState("ACTIVE"), # TSEQ transmitted.
),
@ -234,7 +236,7 @@ class PollingFSM(FSM):
# Link Training and Status State Machine -----------------------------------------------------------
class LTSSM(Module):
def __init__(self, lfps_unit, ts_unit):
def __init__(self, serdes, lfps_unit, ts_unit):
# SS Inactive FSM --------------------------------------------------------------------------
self.submodules.ss_inactive_fsm = SSInactiveFSM()
@ -243,6 +245,7 @@ class LTSSM(Module):
# Polling FSM ------------------------------------------------------------------------------
self.submodules.polling_fsm = PollingFSM(
serdes = serdes,
lfps_unit = lfps_unit,
ts_unit = ts_unit)
self.comb += self.polling_fsm.reset.eq(lfps_unit.rx_polling)

12
usb3_pipe/phy.py
View File

@ -14,8 +14,8 @@ from usb3_pipe.ltssm import LTSSM
class USB3PHY(Module):
def __init__(self, serdes, sys_clk_freq):
assert sys_clk_freq > 125e6
self.enable = Signal() # i
self.ready = Signal() # o
self.enable = Signal(reset=1) # i
self.ready = Signal() # o
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -24,14 +24,20 @@ class USB3PHY(Module):
# LFPS -------------------------------------------------------------------------------------
lfps = LFPSUnit(sys_clk_freq=sys_clk_freq, serdes=serdes)
lfps = ResetInserter()(lfps)
self.comb += lfps.reset.eq(~self.enable)
self.submodules.lfps = lfps
# TS----------------------------------------------------------------------------------------
ts = TSUnit(serdes=serdes)
ts = ResetInserter()(ts)
self.comb += ts.reset.eq(~self.enable)
self.submodules.ts = ts
# LTSSM ------------------------------------------------------------------------------------
ltssm = LTSSM(lfps_unit=lfps, ts_unit=ts)
ltssm = LTSSM(serdes=serdes, lfps_unit=lfps, ts_unit=ts)
ltssm = ResetInserter()(ltssm)
self.comb += ltssm.reset.eq(~self.enable)
self.submodules.ltssm = ltssm
self.comb += self.ready.eq(ltssm.polling_fsm.idle)

12
usb3_pipe/serdes.py
View File

@ -105,7 +105,7 @@ class K7USB3SerDes(Module):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.enable = Signal() # i
self.enable = Signal(reset=1) # i
self.ready = Signal() # o
self.tx_polarity = Signal() # i
@ -149,13 +149,13 @@ class K7USB3SerDes(Module):
gtx.add_stream_endpoints()
tx_datapath = SerdesTXDatapath("tx")
rx_datapath = SerdesRXDatapath("rx")
rx_aligner = SerdesRXAligner()
rx_aligner = SerdesRXWordAligner()
self.submodules += gtx, tx_datapath, rx_datapath, rx_aligner
self.comb += [
gtx.tx_enable.eq(self.enable),
gtx.rx_enable.eq(self.enable),
self.ready.eq(gtx.tx_ready & gtx.rx_ready),
gtx.rx_align.eq(0),
gtx.rx_align.eq(self.rx_align),
rx_aligner.enable.eq(self.rx_align),
self.sink.connect(tx_datapath.sink),
tx_datapath.source.connect(gtx.sink),
@ -194,7 +194,7 @@ class A7USB3SerDes(Module):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.source = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.enable = Signal() # i
self.enable = Signal(reset=1) # i
self.ready = Signal() # o
self.tx_polarity = Signal() # i
@ -238,13 +238,13 @@ class A7USB3SerDes(Module):
gtp.add_stream_endpoints()
tx_datapath = SerdesTXDatapath("tx")
rx_datapath = SerdesRXDatapath("rx")
rx_aligner = SerdesRXCommaAligner()
rx_aligner = SerdesRXWordAligner()
self.submodules += gtp, tx_datapath, rx_datapath, rx_aligner
self.comb += [
gtp.tx_enable.eq(self.enable),
gtp.rx_enable.eq(self.enable),
self.ready.eq(gtp.tx_ready & gtp.rx_ready),
gtp.rx_align.eq(0),
gtp.rx_align.eq(self.rx_align),
rx_aligner.enable.eq(self.rx_align),
self.sink.connect(tx_datapath.sink),
tx_datapath.source.connect(gtp.sink),