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targets: Remove add_csr calls (no longer required).

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This commit is contained in:
Florent Kermarrec 2021-05-05 09:49:10 +02:00
parent 45d947cc1c
commit 3d0bea4453
3 changed files with 0 additions and 6 deletions
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2
kc705.py
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@ -123,7 +123,6 @@ class USB3SoC(SoCMini):
usb3_core.source.connect(usb3_pipe.sink), usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready), usb3_core.reset.eq(~usb3_pipe.ready),
] ]
self.add_csr("usb3_core")
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready) self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
@ -162,7 +161,6 @@ class USB3SoC(SoCMini):
usb3_pipe.sink, usb3_pipe.sink,
] ]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv") self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

2
netv2.py
View File

@ -93,7 +93,6 @@ class USB3SoC(SoCMini):
usb3_core.source.connect(usb3_pipe.sink), usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready), usb3_core.reset.eq(~usb3_pipe.ready),
] ]
self.add_csr("usb3_core")
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready) self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
@ -132,7 +131,6 @@ class USB3SoC(SoCMini):
usb3_pipe.sink, usb3_pipe.sink,
] ]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv") self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------

2
versa_ecp5.py
View File

@ -124,7 +124,6 @@ class USB3SoC(SoCMini):
usb3_core.source.connect(usb3_pipe.sink), usb3_core.source.connect(usb3_pipe.sink),
usb3_core.reset.eq(~usb3_pipe.ready), usb3_core.reset.eq(~usb3_pipe.ready),
] ]
self.add_csr("usb3_core")
# Leds ------------------------------------------------------------------------------------- # Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(~usb3_serdes.ready) self.comb += platform.request("user_led", 0).eq(~usb3_serdes.ready)
@ -163,7 +162,6 @@ class USB3SoC(SoCMini):
usb3_pipe.sink, usb3_pipe.sink,
] ]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv") self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, csr_csv="tools/analyzer.csv")
self.add_csr("analyzer")
# Build -------------------------------------------------------------------------------------------- # Build --------------------------------------------------------------------------------------------