FPGA/usb3_pipe
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usb3_pipe/core: sys_clk_freq >= 125MHz

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This commit is contained in:
Florent Kermarrec 2019-12-04 07:45:16 +01:00
parent 27e6f389c8
commit 4410383f89
1 changed files with 1 additions and 1 deletions
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2
usb3_pipe/core.py
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@ -17,7 +17,7 @@ from usb3_pipe.serdes import RXWordAligner
@ResetInserter()
class USB3PIPE(Module):
def __init__(self, serdes, sys_clk_freq, with_scrambling=True, with_endianness_swap=True):
assert sys_clk_freq > 125e6
assert sys_clk_freq >= 125e6
self.ready = Signal() # o
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])