mirror of
https://github.com/enjoy-digital/usb3_pipe.git
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usb3_core: continue integration with USB3PIPE
This commit is contained in:
Florent Kermarrec
parent
4d2adbd4bf
commit
480490a48e
@ -1,9 +1,49 @@
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# This file is Copyright (c) 2017-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os
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from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import stream
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# USB3 Core Control --------------------------------------------------------------------------------
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class USB3CoreControl(Module, AutoCSR):
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def __init__(self):
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# Not functional but prevents synthesis optimizations
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self._buf_in_addr = CSRStorage(9)
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self._buf_in_data = CSRStorage(32)
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self._buf_in_wren = CSR()
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self._buf_in_request = CSRStatus()
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self._buf_in_ready = CSRStatus()
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self._buf_in_commit = CSR()
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self._buf_in_commit_len = CSRStorage(11)
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self._buf_in_commit_ack = CSRStatus()
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self._buf_out_addr = CSRStorage(9)
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self._buf_out_q = CSRStatus(32)
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self._buf_out_len = CSRStatus(11)
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self._buf_out_hasdata = CSRStatus()
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self._buf_out_arm = CSR()
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self._buf_out_arm_ack = CSRStatus()
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# # #
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self.buf_in_addr = self._buf_in_addr.storage
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self.buf_in_data = self._buf_in_data.storage
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self.buf_in_wren = self._buf_in_wren.re & self._buf_in_wren.r
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self.buf_in_request = self._buf_in_request.status
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self.buf_in_ready = self._buf_in_ready.status
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self.buf_in_commit = self._buf_in_commit.re & self._buf_in_commit.r
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self.buf_in_commit_len = self._buf_in_commit_len.storage
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self.buf_in_commit_ack = self._buf_in_commit_ack.status
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self.buf_out_addr = self._buf_out_addr.storage
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self.buf_out_q = self._buf_out_q.status
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self.buf_out_len = self._buf_out_len.status
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self.buf_out_hasdata = self._buf_out_hasdata.status
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self.buf_out_arm = self._buf_out_arm.re & self._buf_out_arm.r
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self.buf_out_arm_ack = self._buf_out_arm_ack.status
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# USB3 Core ----------------------------------------------------------------------------------------
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@ -15,47 +55,10 @@ class USB3Core(Module, AutoCSR):
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# # #
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class USB3Control(Module, AutoCSR):
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def __init__(self):
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# Not functional but prevents synthesis optimizations
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self._buf_in_addr = CSRStorage(9)
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self._buf_in_data = CSRStorage(32)
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self._buf_in_wren = CSR()
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self._buf_in_request = CSRStatus()
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self._buf_in_ready = CSRStatus()
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self._buf_in_commit = CSR()
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self._buf_in_commit_len = CSRStorage(11)
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self._buf_in_commit_ack = CSRStatus()
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self._buf_out_addr = CSRStorage(9)
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self._buf_out_q = CSRStatus(32)
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self._buf_out_len = CSRStatus(11)
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self._buf_out_hasdata = CSRStatus()
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self._buf_out_arm = CSR()
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self._buf_out_arm_ack = CSRStatus()
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self.submodules.usb3_control = usb3_control = USB3CoreControl()
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# # #
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self.phy_enable = self._phy_enable.storage
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self.core_enable = self._core_enable.storage
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self.buf_in_addr = self._buf_in_addr.storage
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self.buf_in_data = self._buf_in_data.storage
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self.buf_in_wren = self._buf_in_wren.re & self._buf_in_wren.r
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self.buf_in_request = self._buf_in_request.status
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self.buf_in_ready = self._buf_in_ready.status
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self.buf_in_commit = self._buf_in_commit.re & self._buf_in_commit.r
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self.buf_in_commit_len = self._buf_in_commit_len.storage
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self.buf_in_commit_ack = self._buf_in_commit_ack.status
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self.buf_out_addr = self._buf_out_addr.storage
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self.buf_out_q = self._buf_out_q.status
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self.buf_out_len = self._buf_out_len.status
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self.buf_out_hasdata = self._buf_out_hasdata.status
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self.buf_out_arm = self._buf_out_arm.re & self._buf_out_arm.r
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self.buf_out_arm_ack = self._buf_out_arm_ack.status
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self.submodules.usb3_control = USB3Control()
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self.specials += Instance("usb3_top",
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self.comb += sink.ready.eq(1)
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self.specials += Instance("usb3_top_usb3_pipe",
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i_clk = ClockSignal(),
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i_reset_n = ~self.reset,
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@ -64,31 +67,31 @@ class USB3Core(Module, AutoCSR):
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i_in_active = sink.valid,
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o_out_data = source.data,
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o_out_datak = source.datak,
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o_out_datak = source.ctrl,
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o_out_active = source.valid,
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i_out_stall = ~source.ready,
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i_buf_in_addr = self.usb3_control.buf_in_addr,
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i_buf_in_data = self.usb3_control.buf_in_data,
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i_buf_in_wren = self.usb3_control.buf_in_wren,
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o_buf_in_request = self.usb3_control.buf_in_request,
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o_buf_in_ready = self.usb3_control.buf_in_ready,
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i_buf_in_commit = self.usb3_control.buf_in_commit,
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i_buf_in_commit_len = self.usb3_control.buf_in_commit_len,
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o_buf_in_commit_ack = self.usb3_control.buf_in_commit_ack,
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i_buf_in_addr = usb3_control.buf_in_addr,
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i_buf_in_data = usb3_control.buf_in_data,
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i_buf_in_wren = usb3_control.buf_in_wren,
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o_buf_in_request = usb3_control.buf_in_request,
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o_buf_in_ready = usb3_control.buf_in_ready,
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i_buf_in_commit = usb3_control.buf_in_commit,
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i_buf_in_commit_len = usb3_control.buf_in_commit_len,
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o_buf_in_commit_ack = usb3_control.buf_in_commit_ack,
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i_buf_out_addr = self.usb3_control.buf_out_addr,
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o_buf_out_q = self.usb3_control.buf_out_q,
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o_buf_out_len = self.usb3_control.buf_out_len,
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o_buf_out_hasdata = self.usb3_control.buf_out_hasdata,
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i_buf_out_arm = self.usb3_control.buf_out_arm,
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o_buf_out_arm_ack = self.usb3_control.buf_out_arm_ack,
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i_buf_out_addr = usb3_control.buf_out_addr,
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o_buf_out_q = usb3_control.buf_out_q,
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o_buf_out_len = usb3_control.buf_out_len,
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o_buf_out_hasdata = usb3_control.buf_out_hasdata,
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i_buf_out_arm = usb3_control.buf_out_arm,
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o_buf_out_arm_ack = usb3_control.buf_out_arm_ack,
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#o_vend_req_act =,
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#o_vend_req_request =,
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#o_vend_req_val =
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)
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daisho_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "daisho")
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platform.add_verilog_include_path(os.path.join(daisho_path, "core"))
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platform.add_verilog_include_path(os.path.join(daisho_path, "core", "usb3"))
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platform.add_source_dir(os.path.join(daisho_path, "core", "usb3"))
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platform.add_verilog_include_path(os.path.join(daisho_path))
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platform.add_verilog_include_path(os.path.join(daisho_path, "usb3"))
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platform.add_source_dir(os.path.join(daisho_path, "usb3"))
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@ -44,6 +44,8 @@ output wire [7:0] vend_req_request,
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output wire [15:0] vend_req_val
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);
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`include "usb3_const.vh"
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////////////////////////////////////////////////////////////
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//
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// USB 3.0 Link layer interface
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@ -55,8 +57,8 @@ usb3_link iu3l (
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.local_clk ( clk ),
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.reset_n ( reset_n ),
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.ltssm_state ( ), // FIXME
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.ltssm_hot_reset ( ), // FIXME
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.ltssm_state ( LT_U0 ), // FIXME ?
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.ltssm_hot_reset ( 1'b0 ),
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.ltssm_go_disabled ( ),
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.ltssm_go_recovery ( ),
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.ltssm_go_u ( ),
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@ -252,7 +254,7 @@ usb3_protocol iu3r (
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.ext_clk ( clk ), // FIXME ?
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.reset_n ( reset_n),
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.ltssm_state ( ), // FIXME
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.ltssm_state ( LT_U0 ), // FIXME ?
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// muxed endpoint signals
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.endp_mode_rx ( prot_endp_mode_rx ),
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