diff --git a/usb3_core/core.py b/usb3_core/core.py index 962fcfa..3227b04 100644 --- a/usb3_core/core.py +++ b/usb3_core/core.py @@ -1,9 +1,49 @@ # This file is Copyright (c) 2017-2019 Florent Kermarrec # License: BSD +import os + from migen import * from litex.soc.interconnect.csr import * +from litex.soc.interconnect import stream + +# USB3 Core Control -------------------------------------------------------------------------------- + +class USB3CoreControl(Module, AutoCSR): + def __init__(self): + # Not functional but prevents synthesis optimizations + self._buf_in_addr = CSRStorage(9) + self._buf_in_data = CSRStorage(32) + self._buf_in_wren = CSR() + self._buf_in_request = CSRStatus() + self._buf_in_ready = CSRStatus() + self._buf_in_commit = CSR() + self._buf_in_commit_len = CSRStorage(11) + self._buf_in_commit_ack = CSRStatus() + self._buf_out_addr = CSRStorage(9) + self._buf_out_q = CSRStatus(32) + self._buf_out_len = CSRStatus(11) + self._buf_out_hasdata = CSRStatus() + self._buf_out_arm = CSR() + self._buf_out_arm_ack = CSRStatus() + + # # # + + self.buf_in_addr = self._buf_in_addr.storage + self.buf_in_data = self._buf_in_data.storage + self.buf_in_wren = self._buf_in_wren.re & self._buf_in_wren.r + self.buf_in_request = self._buf_in_request.status + self.buf_in_ready = self._buf_in_ready.status + self.buf_in_commit = self._buf_in_commit.re & self._buf_in_commit.r + self.buf_in_commit_len = self._buf_in_commit_len.storage + self.buf_in_commit_ack = self._buf_in_commit_ack.status + self.buf_out_addr = self._buf_out_addr.storage + self.buf_out_q = self._buf_out_q.status + self.buf_out_len = self._buf_out_len.status + self.buf_out_hasdata = self._buf_out_hasdata.status + self.buf_out_arm = self._buf_out_arm.re & self._buf_out_arm.r + self.buf_out_arm_ack = self._buf_out_arm_ack.status # USB3 Core ---------------------------------------------------------------------------------------- @@ -15,47 +55,10 @@ class USB3Core(Module, AutoCSR): # # # - class USB3Control(Module, AutoCSR): - def __init__(self): - # Not functional but prevents synthesis optimizations - self._buf_in_addr = CSRStorage(9) - self._buf_in_data = CSRStorage(32) - self._buf_in_wren = CSR() - self._buf_in_request = CSRStatus() - self._buf_in_ready = CSRStatus() - self._buf_in_commit = CSR() - self._buf_in_commit_len = CSRStorage(11) - self._buf_in_commit_ack = CSRStatus() - self._buf_out_addr = CSRStorage(9) - self._buf_out_q = CSRStatus(32) - self._buf_out_len = CSRStatus(11) - self._buf_out_hasdata = CSRStatus() - self._buf_out_arm = CSR() - self._buf_out_arm_ack = CSRStatus() + self.submodules.usb3_control = usb3_control = USB3CoreControl() - # # # - - self.phy_enable = self._phy_enable.storage - self.core_enable = self._core_enable.storage - self.buf_in_addr = self._buf_in_addr.storage - self.buf_in_data = self._buf_in_data.storage - self.buf_in_wren = self._buf_in_wren.re & self._buf_in_wren.r - self.buf_in_request = self._buf_in_request.status - self.buf_in_ready = self._buf_in_ready.status - self.buf_in_commit = self._buf_in_commit.re & self._buf_in_commit.r - self.buf_in_commit_len = self._buf_in_commit_len.storage - self.buf_in_commit_ack = self._buf_in_commit_ack.status - self.buf_out_addr = self._buf_out_addr.storage - self.buf_out_q = self._buf_out_q.status - self.buf_out_len = self._buf_out_len.status - self.buf_out_hasdata = self._buf_out_hasdata.status - self.buf_out_arm = self._buf_out_arm.re & self._buf_out_arm.r - self.buf_out_arm_ack = self._buf_out_arm_ack.status - - - self.submodules.usb3_control = USB3Control() - - self.specials += Instance("usb3_top", + self.comb += sink.ready.eq(1) + self.specials += Instance("usb3_top_usb3_pipe", i_clk = ClockSignal(), i_reset_n = ~self.reset, @@ -64,31 +67,31 @@ class USB3Core(Module, AutoCSR): i_in_active = sink.valid, o_out_data = source.data, - o_out_datak = source.datak, + o_out_datak = source.ctrl, o_out_active = source.valid, i_out_stall = ~source.ready, - i_buf_in_addr = self.usb3_control.buf_in_addr, - i_buf_in_data = self.usb3_control.buf_in_data, - i_buf_in_wren = self.usb3_control.buf_in_wren, - o_buf_in_request = self.usb3_control.buf_in_request, - o_buf_in_ready = self.usb3_control.buf_in_ready, - i_buf_in_commit = self.usb3_control.buf_in_commit, - i_buf_in_commit_len = self.usb3_control.buf_in_commit_len, - o_buf_in_commit_ack = self.usb3_control.buf_in_commit_ack, + i_buf_in_addr = usb3_control.buf_in_addr, + i_buf_in_data = usb3_control.buf_in_data, + i_buf_in_wren = usb3_control.buf_in_wren, + o_buf_in_request = usb3_control.buf_in_request, + o_buf_in_ready = usb3_control.buf_in_ready, + i_buf_in_commit = usb3_control.buf_in_commit, + i_buf_in_commit_len = usb3_control.buf_in_commit_len, + o_buf_in_commit_ack = usb3_control.buf_in_commit_ack, - i_buf_out_addr = self.usb3_control.buf_out_addr, - o_buf_out_q = self.usb3_control.buf_out_q, - o_buf_out_len = self.usb3_control.buf_out_len, - o_buf_out_hasdata = self.usb3_control.buf_out_hasdata, - i_buf_out_arm = self.usb3_control.buf_out_arm, - o_buf_out_arm_ack = self.usb3_control.buf_out_arm_ack, + i_buf_out_addr = usb3_control.buf_out_addr, + o_buf_out_q = usb3_control.buf_out_q, + o_buf_out_len = usb3_control.buf_out_len, + o_buf_out_hasdata = usb3_control.buf_out_hasdata, + i_buf_out_arm = usb3_control.buf_out_arm, + o_buf_out_arm_ack = usb3_control.buf_out_arm_ack, #o_vend_req_act =, #o_vend_req_request =, #o_vend_req_val = ) daisho_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "daisho") - platform.add_verilog_include_path(os.path.join(daisho_path, "core")) - platform.add_verilog_include_path(os.path.join(daisho_path, "core", "usb3")) - platform.add_source_dir(os.path.join(daisho_path, "core", "usb3")) + platform.add_verilog_include_path(os.path.join(daisho_path)) + platform.add_verilog_include_path(os.path.join(daisho_path, "usb3")) + platform.add_source_dir(os.path.join(daisho_path, "usb3")) diff --git a/usb3_core/daisho/usb3/usb3_top_usb3_pipe.v b/usb3_core/daisho/usb3/usb3_top_usb3_pipe.v index 0914145..05343c0 100644 --- a/usb3_core/daisho/usb3/usb3_top_usb3_pipe.v +++ b/usb3_core/daisho/usb3/usb3_top_usb3_pipe.v @@ -44,6 +44,8 @@ output wire [7:0] vend_req_request, output wire [15:0] vend_req_val ); +`include "usb3_const.vh" + //////////////////////////////////////////////////////////// // // USB 3.0 Link layer interface @@ -55,8 +57,8 @@ usb3_link iu3l ( .local_clk ( clk ), .reset_n ( reset_n ), - .ltssm_state ( ), // FIXME - .ltssm_hot_reset ( ), // FIXME + .ltssm_state ( LT_U0 ), // FIXME ? + .ltssm_hot_reset ( 1'b0 ), .ltssm_go_disabled ( ), .ltssm_go_recovery ( ), .ltssm_go_u ( ), @@ -252,7 +254,7 @@ usb3_protocol iu3r ( .ext_clk ( clk ), // FIXME ? .reset_n ( reset_n), - .ltssm_state ( ), // FIXME + .ltssm_state ( LT_U0 ), // FIXME ? // muxed endpoint signals .endp_mode_rx ( prot_endp_mode_rx ),