mirror of
https://github.com/enjoy-digital/usb3_pipe.git
synced 2025-01-04 10:18:41 +08:00
usb3_core: first usb3_top simplifications to use USB3PIPE
This commit is contained in:
Florent Kermarrec
parent
f926443335
commit
4d2adbd4bf
@ -9,6 +9,7 @@ from litex.soc.interconnect.csr import *
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class USB3Core(Module, AutoCSR):
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def __init__(self, platform):
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self.reset = Signal()
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self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
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self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
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@ -54,51 +55,18 @@ class USB3Core(Module, AutoCSR):
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self.submodules.usb3_control = USB3Control()
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phy_rx_status = Signal(6)
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phy_phy_status = Signal(2)
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dbg_pipe_state = Signal(6)
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dbg_ltssm_state = Signal(5)
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usb_pipe_status_phy_status = Signal()
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self.specials += Tristate(usb_pipe_status.phy_status, 0, ~usb3_reset_n, usb_pipe_status_phy_status)
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self.comb += usb3_reset_n.eq(self.usb3_control.phy_enable)
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self.specials += Instance("usb3_top",
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i_ext_clk = ClockSignal(),
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i_reset_n = self.usb3_control.core_enable,
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i_clk = ClockSignal(),
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i_reset_n = ~self.reset,
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i_phy_pipe_half_clk = 0, # FIXME
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i_phy_pipe_half_clk_phase = 0, # FIXME,
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i_phy_pipe_quarter_clk = 0, # FIXME,
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i_in_data = sink.data,
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i_in_datak = sink.ctrl,
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i_in_active = sink.valid,
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i_phy_pipe_rx_data = sink.data,
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i_phy_pipe_rx_datak = sink.ctrl,
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i_phy_pipe_rx_valid = sink.valid,
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o_phy_pipe_tx_data = source.data, # FIXME use source.ready
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o_phy_pipe_tx_datak = source.ctrl, # FIXME use source.ready
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# FIXME: remove since USB3PIPE is handling this internally
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#o_phy_reset_n = ,
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#o_phy_out_enable = ,
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#o_phy_phy_reset_n = ,
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#o_phy_tx_detrx_lpbk = ,
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#o_phy_tx_elecidle = ,
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#io_phy_rx_elecidle = ,
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#i_phy_rx_status = ,
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#o_phy_power_down = ,
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#i_phy_phy_status_i = ,
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#o_phy_phy_status_o = ,
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#i_phy_pwrpresent = ,
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#o_phy_tx_oneszeros = ,
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#o_phy_tx_deemph = ,
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#o_phy_tx_margin = ,
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#o_phy_tx_swing = ,
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#o_phy_rx_polarity = ,
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#o_phy_rx_termination = ,
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#o_phy_rate = ,
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#o_phy_elas_buf_mode = ,
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o_out_data = source.data,
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o_out_datak = source.datak,
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o_out_active = source.valid,
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i_out_stall = ~source.ready,
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i_buf_in_addr = self.usb3_control.buf_in_addr,
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i_buf_in_data = self.usb3_control.buf_in_data,
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@ -109,19 +77,16 @@ class USB3Core(Module, AutoCSR):
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i_buf_in_commit_len = self.usb3_control.buf_in_commit_len,
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o_buf_in_commit_ack = self.usb3_control.buf_in_commit_ack,
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i_buf_out_addr = self.usb3_control.buf_out_addr,
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o_buf_out_q = self.usb3_control.buf_out_q,
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o_buf_out_len = self.usb3_control.buf_out_len,
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o_buf_out_hasdata = self.usb3_control.buf_out_hasdata,
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i_buf_out_arm = self.usb3_control.buf_out_arm,
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o_buf_out_arm_ack = self.usb3_control.buf_out_arm_ack,
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i_buf_out_addr = self.usb3_control.buf_out_addr,
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o_buf_out_q = self.usb3_control.buf_out_q,
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o_buf_out_len = self.usb3_control.buf_out_len,
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o_buf_out_hasdata = self.usb3_control.buf_out_hasdata,
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i_buf_out_arm = self.usb3_control.buf_out_arm,
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o_buf_out_arm_ack = self.usb3_control.buf_out_arm_ack,
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#o_vend_req_act =,
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#o_vend_req_request =,
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#o_vend_req_val =,
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#o_dbg_pipe_state = ,
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#o_dbg_ltssm_state = ,
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#o_vend_req_val =
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)
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daisho_path = os.path.join(os.path.abspath(os.path.dirname(__file__)), "daisho")
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platform.add_verilog_include_path(os.path.join(daisho_path, "core"))
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@ -11,38 +11,17 @@
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module usb3_top_usb3_pipe (
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input wire ext_clk,
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input wire clk,
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input wire reset_n,
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input wire phy_pipe_half_clk, // 125MHz: 1/2 PCLK
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input wire phy_pipe_half_clk_phase, // 125MHz: 1/2 PCLK, phase shift 90
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input wire phy_pipe_quarter_clk, // 62.5MHz: 1/4 PCLK
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input wire [31:0] phy_pipe_rx_data,
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input wire [3:0] phy_pipe_rx_datak,
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input wire [1:0] phy_pipe_rx_valid,
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output wire [31:0] phy_pipe_tx_data,
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output wire [3:0] phy_pipe_tx_datak,
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input wire [31:0] in_data,
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input wire [3:0] in_datak,
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input wire in_active,
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output wire phy_reset_n,
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output wire phy_out_enable,
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output wire phy_phy_reset_n,
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output wire phy_tx_detrx_lpbk,
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output wire phy_tx_elecidle,
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inout wire phy_rx_elecidle,
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input wire [5:0] phy_rx_status,
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output wire [1:0] phy_power_down,
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input wire [1:0] phy_phy_status_i,
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output wire phy_phy_status_o,
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input wire phy_pwrpresent,
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output wire phy_tx_oneszeros,
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output wire [1:0] phy_tx_deemph,
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output wire [2:0] phy_tx_margin,
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output wire phy_tx_swing,
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output wire phy_rx_polarity,
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output wire phy_rx_termination,
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output wire phy_rate,
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output wire phy_elas_buf_mode,
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output wire [31:0] out_data,
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output wire [3:0] out_datak,
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output wire out_active,
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output wire out_stall,
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input wire [8:0] buf_in_addr,
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input wire [31:0] buf_in_data,
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@ -62,246 +41,33 @@ output wire buf_out_arm_ack,
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output wire vend_req_act,
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output wire [7:0] vend_req_request,
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output wire [15:0] vend_req_val,
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output wire [5:0] dbg_pipe_state,
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output wire [4:0] dbg_ltssm_state
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output wire [15:0] vend_req_val
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);
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reg reset_1, reset_2; // local reset
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wire local_reset = reset_n & phy_pwrpresent;
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always @(posedge phy_pipe_half_clk ) begin
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// synchronize external reset to local domain
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{reset_2, reset_1} <= {reset_1, local_reset};
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end
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assign phy_reset_n = reset_n; // TUSB1310A has minimum 1uS pulse width for RESET
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// responsibility of the toplevel module to supply this reset
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// NOTE: reset entire phy will cause loss of PLL lock
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assign phy_phy_reset_n = reset_n & phy_pwrpresent;
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// reset the PHY along with all our core code if cable unplugged
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assign phy_out_enable = 1'b1;
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wire [1:0] mux_tx_margin;
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parameter XTAL_SEL = 1'b0; // crystal input
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parameter OSC_SEL = 1'b1; // clock input
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parameter [2:0] SSC_DIS = 2'b11; // spread spectrum clock disable
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parameter [2:0] SSC_EN = 2'b00; // spread spectrum clock enable
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parameter PIPE_16BIT = 1'b0; // sdr 16bit pipe interface
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// strap pins
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assign phy_rx_elecidle = reset_2 ? 1'bZ : XTAL_SEL;
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assign phy_tx_margin = reset_2 ? mux_tx_margin : SSC_DIS;
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assign phy_phy_status_o = reset_2 ? 1'bZ : PIPE_16BIT;
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////////////////////////////////////////////////////////////
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//
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// USB 3.0 PIPE3 interface
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//
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////////////////////////////////////////////////////////////
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wire ltssm_reset_n;
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usb3_pipe iu3p (
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.slow_clk ( phy_pipe_quarter_clk ),
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.local_clk ( phy_pipe_half_clk ),
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.local_clk_capture ( phy_pipe_half_clk_phase ),
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.reset_n ( reset_2 ),
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.ltssm_reset_n ( ltssm_reset_n ),
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.phy_pipe_rx_data ( phy_pipe_rx_data ),
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.phy_pipe_rx_datak ( phy_pipe_rx_datak ),
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.phy_pipe_rx_valid ( phy_pipe_rx_valid ),
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.phy_pipe_tx_data ( phy_pipe_tx_data ),
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.phy_pipe_tx_datak ( phy_pipe_tx_datak ),
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.phy_tx_detrx_lpbk ( phy_tx_detrx_lpbk ),
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.phy_tx_elecidle ( phy_tx_elecidle ),
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.phy_rx_elecidle ( phy_rx_elecidle ),
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.phy_rx_status ( phy_rx_status ),
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.phy_power_down ( phy_power_down ),
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.phy_phy_status ( phy_phy_status_i ),
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.phy_pwrpresent ( phy_pwrpresent ),
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.phy_tx_oneszeros ( phy_tx_oneszeros ),
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.phy_tx_deemph ( phy_tx_deemph ),
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.phy_tx_margin ( mux_tx_margin ),
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.phy_tx_swing ( phy_tx_swing ),
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.phy_rx_polarity ( phy_rx_polarity ),
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.phy_rx_termination ( phy_rx_termination ),
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.phy_rate ( phy_rate ),
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.phy_elas_buf_mode ( phy_elas_buf_mode ),
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.link_in_data ( link_in_data ),
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.link_in_datak ( link_in_datak ),
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.link_in_active ( link_in_active ),
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.link_out_data ( link_out_data ),
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.link_out_datak ( link_out_datak ),
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.link_out_active ( link_out_active ),
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.link_out_stall ( link_out_stall ),
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.partner_detect ( partner_detect ),
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.partner_looking ( partner_looking ),
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.partner_detected ( partner_detected ),
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.ltssm_tx_detrx_lpbk ( port_tx_detrx_lpbk ),
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.ltssm_tx_elecidle ( port_tx_elecidle ),
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.ltssm_power_down ( port_power_down ),
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.ltssm_power_go ( port_power_go ),
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.ltssm_power_ack ( port_power_ack ),
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.ltssm_hot_reset ( ltssm_hot_reset ),
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.ltssm_state ( ltssm_state ),
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.ltssm_training ( ltssm_training ),
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.ltssm_train_rxeq ( ltssm_train_rxeq ),
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.ltssm_train_rxeq_pass ( ltssm_train_rxeq_pass ),
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.ltssm_train_active ( ltssm_train_active ),
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.ltssm_train_ts1 ( ltssm_train_ts1 ),
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.ltssm_train_ts2 ( ltssm_train_ts2 ),
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.ltssm_train_config ( ltssm_train_config ),
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.ltssm_train_idle ( ltssm_train_idle ),
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.ltssm_train_idle_pass ( ltssm_train_idle_pass ),
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.lfps_recv_active ( lfps_recv_active ),
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.lfps_recv_poll_u1 ( lfps_recv_poll_u1 ),
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.lfps_recv_ping ( lfps_recv_ping ),
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.lfps_recv_reset ( lfps_recv_reset ),
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.lfps_recv_u2lb ( lfps_recv_u2lb ),
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.lfps_recv_u3 ( lfps_recv_u3 ),
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.dbg_state ( dbg_pipe_state )
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);
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////////////////////////////////////////////////////////////
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//
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// USB 3.0 LTSSM, LFPS
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//
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////////////////////////////////////////////////////////////
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wire [4:0] ltssm_state;
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wire port_rx_term;
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wire port_tx_detrx_lpbk;
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wire port_tx_elecidle;
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wire [1:0] port_power_down;
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wire port_power_go;
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wire port_power_ack;
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wire port_power_err;
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wire ltssm_hot_reset;
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wire ltssm_training;
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wire ltssm_train_rxeq;
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wire ltssm_train_rxeq_pass;
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wire ltssm_train_active;
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wire ltssm_train_ts1;
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wire ltssm_train_ts2;
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wire ltssm_train_config;
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wire ltssm_train_idle;
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wire ltssm_train_idle_pass;
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wire partner_detect;
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wire partner_looking;
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wire partner_detected;
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wire lfps_recv_active;
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wire lfps_recv_poll_u1;
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wire lfps_recv_ping;
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wire lfps_recv_reset;
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wire lfps_recv_u2lb;
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wire lfps_recv_u3;
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wire ltssm_warm_reset;
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usb3_ltssm iu3lt (
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.slow_clk ( phy_pipe_quarter_clk ),
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.local_clk ( phy_pipe_half_clk ),
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.reset_n ( ltssm_reset_n ),
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// inputs
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.vbus_present ( phy_pwrpresent ),
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.port_rx_valid ( phy_pipe_rx_valid ), // these signals are in the 250mhz source
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.port_rx_elecidle ( phy_rx_elecidle ), // domain, but no problem for lfps in 62.5mhz
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.partner_looking ( partner_looking ),
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.partner_detected ( partner_detected ),
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.port_power_state ( phy_power_down ), // reflect actual value driven by PIPE pd_fsm
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.port_power_ack ( port_power_ack ),
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.port_power_err ( port_power_err ),
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.train_rxeq_pass ( ltssm_train_rxeq_pass ),
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.train_idle_pass ( ltssm_train_idle_pass ),
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.train_ts1 ( ltssm_train_ts1 ),
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.train_ts2 ( ltssm_train_ts2 ),
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.go_disabled ( ltssm_go_disabled ),
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.go_recovery ( ltssm_go_recovery ),
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.go_u ( ltssm_go_u ),
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.hot_reset ( ltssm_hot_reset ),
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// outputs
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.ltssm_state ( ltssm_state ),
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.port_rx_term ( port_rx_term ),
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.port_tx_detrx_lpbk ( port_tx_detrx_lpbk ),
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.port_tx_elecidle ( port_tx_elecidle ),
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.port_power_down ( port_power_down ),
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.port_power_go ( port_power_go ),
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.partner_detect ( partner_detect ),
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.training ( ltssm_training ),
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.train_rxeq ( ltssm_train_rxeq ),
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.train_active ( ltssm_train_active ),
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.train_config ( ltssm_train_config ),
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.train_idle ( ltssm_train_idle ),
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.lfps_recv_active ( lfps_recv_active ),
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.lfps_recv_poll_u1 ( lfps_recv_poll_u1 ),
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.lfps_recv_ping ( lfps_recv_ping ),
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.lfps_recv_reset ( lfps_recv_reset ),
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.lfps_recv_u2lb ( lfps_recv_u2lb ),
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.lfps_recv_u3 ( lfps_recv_u3 ),
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.warm_reset ( ltssm_warm_reset ),
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.dbg_state ( dbg_ltssm_state )
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);
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////////////////////////////////////////////////////////////
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//
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// USB 3.0 Link layer interface
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//
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////////////////////////////////////////////////////////////
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wire [31:0] link_in_data;
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wire [3:0] link_in_datak;
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wire link_in_active;
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wire [31:0] link_out_data;
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wire [3:0] link_out_datak;
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wire link_out_active;
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wire link_out_stall;
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wire ltssm_go_disabled;
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wire ltssm_go_recovery;
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wire [2:0] ltssm_go_u;
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usb3_link iu3l (
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.local_clk ( phy_pipe_half_clk ),
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.reset_n ( reset_2 ),
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.local_clk ( clk ),
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.reset_n ( reset_n ),
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.ltssm_state ( ltssm_state ),
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.ltssm_hot_reset ( ltssm_hot_reset ),
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.ltssm_go_disabled ( ltssm_go_disabled ),
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.ltssm_go_recovery ( ltssm_go_recovery ),
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.ltssm_go_u ( ltssm_go_u),
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.in_data ( link_in_data ),
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.in_datak ( link_in_datak ),
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.in_active ( link_in_active ),
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.ltssm_state ( ), // FIXME
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.ltssm_hot_reset ( ), // FIXME
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.ltssm_go_disabled ( ),
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.ltssm_go_recovery ( ),
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.ltssm_go_u ( ),
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.in_data ( in_data ),
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.in_datak ( in_datak ),
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.in_active ( in_active ),
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.outp_data ( link_out_data ),
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.outp_datak ( link_out_datak ),
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.outp_active ( link_out_active ),
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.out_stall ( link_out_stall ),
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.outp_data ( out_data ),
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.outp_datak ( out_datak ),
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.outp_active ( out_active ),
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.out_stall ( out_stall ),
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.endp_mode_rx ( prot_endp_mode_rx ),
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.endp_mode_tx ( prot_endp_mode_tx ),
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@ -386,7 +152,6 @@ usb3_link iu3l (
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);
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|
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|
||||
|
||||
////////////////////////////////////////////////////////////
|
||||
//
|
||||
// USB 3.0 Protocol layer interface
|
||||
@ -482,12 +247,12 @@ usb3_link iu3l (
|
||||
|
||||
usb3_protocol iu3r (
|
||||
|
||||
.local_clk ( phy_pipe_half_clk ),
|
||||
.slow_clk ( phy_pipe_quarter_clk ),
|
||||
.ext_clk ( ext_clk ),
|
||||
.local_clk ( clk ), // FIXME ?
|
||||
.slow_clk ( clk ), // FIXME ?
|
||||
.ext_clk ( clk ), // FIXME ?
|
||||
|
||||
.reset_n ( reset_2 | ~ltssm_warm_reset),
|
||||
.ltssm_state ( ltssm_state ),
|
||||
.reset_n ( reset_n),
|
||||
.ltssm_state ( ), // FIXME
|
||||
|
||||
// muxed endpoint signals
|
||||
.endp_mode_rx ( prot_endp_mode_rx ),
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user