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usb3_core: simplify out_fifo.sink.valid
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@ -115,12 +115,12 @@ class USB3Core(Module, AutoCSR):
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out_stall = Signal()
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out_active = Signal()
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out_active_d = Signal()
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self.comb += out_fifo.sink.valid.eq(out_active_d)
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self.sync += [
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out_fifo.sink.valid.eq(out_active),
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out_fifo.sink.data.eq(out_data),
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out_fifo.sink.ctrl.eq(out_datak),
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out_active_d.eq(out_active),
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out_fifo.sink.first.eq(out_active & ~ out_active_d),
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out_fifo.sink.first.eq(out_active & ~out_active_d),
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]
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self.comb += out_fifo.sink.last.eq(~out_active & out_active_d)
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