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https://github.com/enjoy-digital/usb3_pipe.git
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sniffer: add visual K28.5 detection
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@ -4,6 +4,7 @@
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# PCIe Screamer with FT601 TX lanes duplicated to PCIe RX lanes for sniffing FT601 --> Host comm
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from migen import *
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from migen.genlib.misc import WaitTimer
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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@ -143,6 +144,23 @@ class USB3Sniffer(SoCMini):
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csr_csv="analyzer.csv")
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self.add_csr("analyzer")
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# Led (Set Led0 if continuous K28.5 are detected) ------------------------------------------
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def K(x, y):
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return (y << 5) | x
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k28_5_timer = WaitTimer(int(250e6*1e-1))
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k28_5_timer = ClockDomainsRenamer("rx")(k28_5_timer)
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self.submodules += k28_5_timer
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self.comb += [
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k28_5_timer.wait.eq(1),
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If(gtp.source.ctrl[0] & (gtp.source.data[:8] == K(28, 5)),
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k28_5_timer.wait.eq(0)
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),
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If(gtp.source.ctrl[1] & (gtp.source.data[8:] == K(28, 5)),
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k28_5_timer.wait.eq(0)
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),
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platform.request("user_led", 0).eq(~k28_5_timer.done)
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]
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# Build --------------------------------------------------------------------------------------------
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def main():
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