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kc705: Add SFP support (Through Xillybus's SFP2USB) and remove HiTechGlobal USB3.0 FMC support.

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This commit is contained in:
Florent Kermarrec 2022-04-26 15:25:44 +02:00
parent 3d0bea4453
commit 55eee1a81f
1 changed files with 12 additions and 12 deletions
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24
kc705.py
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@ -29,17 +29,7 @@ from usb3_core.core import USB3Core
# USB3 IOs -----------------------------------------------------------------------------------------
_usb3_io = [
# HiTechGlobal USB3.0 FMC P3 connector
("usb3_rx", 0,
Subsignal("p", Pins("HPC:DP0_M2C_P")),
Subsignal("n", Pins("HPC:DP0_M2C_N")),
),
("usb3_tx", 0,
Subsignal("p", Pins("HPC:DP0_C2M_P")),
Subsignal("n", Pins("HPC:DP0_C2M_N")),
),
# PCIe
# PCIe / Through PCIsh-to-USB3 breakout board.
("pcie_rx", 0,
Subsignal("p", Pins("M6")),
Subsignal("n", Pins("M5")),
@ -58,6 +48,16 @@ _usb3_io = [
Subsignal("p", Pins("K6")),
Subsignal("n", Pins("K5"))
),
# SFP / Through XillyUSB's SFP2USB.
("sfp_tx", 0,
Subsignal("p", Pins("H2")),
Subsignal("n", Pins("H1")),
),
("sfp_rx", 0,
Subsignal("p", Pins("G4")),
Subsignal("n", Pins("G3")),
),
]
# CRG ----------------------------------------------------------------------------------------------
@ -79,7 +79,7 @@ class _CRG(Module):
# USB3SoC ------------------------------------------------------------------------------------------
class USB3SoC(SoCMini):
def __init__(self, platform, connector="pcie", with_etherbone=True, with_analyzer=True):
def __init__(self, platform, connector="sfp", with_etherbone=True, with_analyzer=True):
sys_clk_freq = int(125e6)
# SoCMini ----------------------------------------------------------------------------------