From 56811680a2e522c86a1bb14886d0145985c8bcc9 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 29 Nov 2019 13:00:15 +0100
Subject: [PATCH] usb3_core: make sure we generate the USB3 descriptors before
 the build or simulation

---
 kc705.py         | 1 +
 pcie_screamer.py | 1 +
 sim.py           | 1 +
 versa_ecp5.py    | 1 +
 4 files changed, 4 insertions(+)

diff --git a/kc705.py b/kc705.py
index c93ff46..eae7b6b 100755
--- a/kc705.py
+++ b/kc705.py
@@ -181,6 +181,7 @@ def load():
 def main():
     if "load" in sys.argv[1:]:
         load()
+    os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
     platform = kc705.Platform()
     platform.add_extension(_usb3_io)
     soc = USB3SoC(platform)
diff --git a/pcie_screamer.py b/pcie_screamer.py
index 79fe7df..aac3c8b 100755
--- a/pcie_screamer.py
+++ b/pcie_screamer.py
@@ -174,6 +174,7 @@ def load():
 def main():
     if "load" in sys.argv[1:]:
         load()
+    os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
     platform = Platform()
     soc = USB3SoC(platform)
     builder = Builder(soc, output_dir="build", csr_csv="tools/csr.csv")
diff --git a/sim.py b/sim.py
index a91dfae..6f56fde 100755
--- a/sim.py
+++ b/sim.py
@@ -198,6 +198,7 @@ def main():
 
     sim_config = SimConfig(default_clk="sys_clk")
 
+    os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
     os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
 
     soc = USB3PIPESim()
diff --git a/versa_ecp5.py b/versa_ecp5.py
index fd294bd..3da441c 100755
--- a/versa_ecp5.py
+++ b/versa_ecp5.py
@@ -208,6 +208,7 @@ jtag newtap ecp5 tap -irlen 8 -expected-id 0x81112043
 def main():
     if "load" in sys.argv[1:]:
         load()
+    os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
     platform = versa_ecp5.Platform(toolchain="trellis")
     platform.add_extension(_usb3_io)
     soc = USB3SoC(platform)