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versa_ecp5: generate 200MHz refclk from PLL

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This commit is contained in:
Florent Kermarrec 2019-12-05 19:32:57 +01:00
parent 9440d7a47e
commit 6b2c27e230
1 changed files with 4 additions and 2 deletions
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6
versa_ecp5.py
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@ -58,6 +58,7 @@ class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
self.clock_domains.cd_ref = ClockDomain(reset_less=True)
# # #
@ -79,6 +80,7 @@ class _CRG(Module):
self.submodules.pll = pll = ECP5PLL()
pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_ref, 200e6)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked | ~rst_n)
# USB3SoC ------------------------------------------------------------------------------------------
@ -125,8 +127,8 @@ class USB3SoC(SoCMini):
usb3_serdes = ECP5USB3SerDes(platform,
sys_clk = self.crg.cd_sys.clk,
sys_clk_freq = sys_clk_freq,
refclk_pads = platform.request("refclk", 1),
refclk_freq = 156.25e6,
refclk_pads = self.crg.cd_ref.clk,
refclk_freq = 200e6,
tx_pads = platform.request(connector + "_tx"),
rx_pads = platform.request(connector + "_rx"),
channel = 0)