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serdes: rename SerdesRXAligner to SerdesRXWordAligner

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This commit is contained in:
Florent Kermarrec 2019-10-08 10:40:58 +02:00
parent ec3b7e9c57
commit 6ebe23f17b
2 changed files with 5 additions and 5 deletions
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6
test/test_serdes.py
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@ -7,7 +7,7 @@ import random
from migen import *
from usb3_pipe.serdes import SerdesTXDatapath, SerdesRXDatapath
from usb3_pipe.serdes import SerdesRXAligner
from usb3_pipe.serdes import SerdesRXWordAligner
class TestSerDes(unittest.TestCase):
@ -53,7 +53,7 @@ class TestSerDes(unittest.TestCase):
self.assertEqual(dut.data_errors, 0)
self.assertEqual(dut.ctrl_errors, 0)
def test_aligner(self):
def test_rx_word_aligner(self):
aligner_datas_input = [
0x030201bc, 0x07060504, 0x0b0a0908, 0x0f0e0d0c,
0x0201bc07, 0x0605040b, 0x0a09080f, 0x0e0d0c13,
@ -99,7 +99,7 @@ class TestSerDes(unittest.TestCase):
dut.ctrls_errors += 1
yield
dut = SerdesRXAligner()
dut = SerdesRXWordAligner()
run_simulation(dut, [generator(dut), checker(dut)])
self.assertEqual(dut.datas_errors, 0)
self.assertEqual(dut.ctrls_errors, 0)

4
usb3_pipe/serdes.py
View File

@ -55,7 +55,7 @@ class SerdesRXDatapath(Module):
# RX Aligner ---------------------------------------------------------------------------------------
class SerdesRXAligner(stream.PipelinedActor):
class SerdesRXWordAligner(stream.PipelinedActor):
def __init__(self):
self.enable = Signal(reset=1)
self.sink = sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
@ -238,7 +238,7 @@ class A7USB3SerDes(Module):
gtp.add_stream_endpoints()
tx_datapath = SerdesTXDatapath("tx")
rx_datapath = SerdesRXDatapath("rx")
rx_aligner = SerdesRXAligner()
rx_aligner = SerdesRXCommaAligner()
self.submodules += gtp, tx_datapath, rx_datapath, rx_aligner
self.comb += [
gtp.tx_enable.eq(self.enable),