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kc705: add idle handshake start trigger

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This commit is contained in:
Florent Kermarrec 2019-10-08 15:06:49 +02:00
parent 949a8628e7
commit 6fe7a56b6b
3 changed files with 24 additions and 3 deletions
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17
kc705.py
View File

@ -66,7 +66,7 @@ class _CRG(Module):
# USB3SoC ------------------------------------------------------------------------------------------
class USB3SoC(SoCMini):
def __init__(self, platform, connector="usb3",
def __init__(self, platform, connector="pcie",
with_etherbone=True, mac_address=0x10e2d5000000, ip_address="192.168.1.50",
with_analyzer=True):
@ -120,6 +120,19 @@ class USB3SoC(SoCMini):
usb3_phy = USB3PHY(serdes=usb3_serdes, sys_clk_freq=sys_clk_freq)
self.submodules += usb3_phy
# Idle handshake trigger--------------------------------------------------------------------
idle_start = Signal()
rx_ts2_error = Signal()
rx_ts2_error_d = Signal()
self.comb += rx_ts2_error.eq(usb3_phy.ts.ts2_checker.error)
self.sync += rx_ts2_error_d.eq(rx_ts2_error)
self.comb += [
If(usb3_phy.ready,
usb3_serdes.source.ready.eq(1),
idle_start.eq(~rx_ts2_error & rx_ts2_error_d),
)
]
# Leds -------------------------------------------------------------------------------------
self.comb += platform.request("user_led", 0).eq(usb3_serdes.ready)
self.comb += platform.request("user_led", 1).eq(usb3_phy.ready)
@ -140,9 +153,11 @@ class USB3SoC(SoCMini):
usb3_phy.ts.rx_ts1,
usb3_phy.ts.rx_ts2,
usb3_phy.ts.tx_ts2,
usb3_phy.ts.ts2_checker.error,
# LTSSM
usb3_phy.ltssm.polling_fsm,
idle_start,
# Endpoints
usb3_serdes.source,

4
tools/test_analyzer.py
View File

@ -22,6 +22,8 @@ def help():
print(" - rx_ts2")
print(" - tx_ts2")
print("")
print(" - idle_start")
print("")
print(" - now")
exit()
@ -62,6 +64,8 @@ elif sys.argv[1] == "rx_ts2":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_rx_ts2" : 1})
elif sys.argv[1] == "tx_ts2":
analyzer.configure_trigger(cond={"soc_usb3_phy_ts_tx_ts2" : 1})
elif sys.argv[1] == "idle_start":
analyzer.configure_trigger(cond={"soc_idle_start" : 1})
elif sys.argv[1] == "now":
analyzer.configure_trigger(cond={})
else:

6
usb3_pipe/training.py
View File

@ -13,6 +13,7 @@ class TSChecker(Module):
def __init__(self, ordered_set, n_ordered_sets):
self.sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
self.detected = Signal() # o
self.error = Signal() # o
if ordered_set.name in ["TS1", "TS2"]:
self.reset = Signal() # o
@ -51,7 +52,8 @@ class TSChecker(Module):
If((self.sink.data & error_mask) != (port.dat_r & error_mask),
error.eq(1)
)
)
),
self.error.eq(error)
]
# Link Config ------------------------------------------------------------------------------
@ -196,7 +198,7 @@ class TSUnit(Module):
serdes.source.connect(tseq_checker.sink, omit={"ready"}),
serdes.source.connect(ts1_checker.sink, omit={"ready"}),
serdes.source.connect(ts2_checker.sink, omit={"ready"}),
serdes.source.ready.eq(self.rx_enable),
If(self.rx_enable, serdes.source.ready.eq(1)),
self.rx_tseq.eq(tseq_checker.detected),
self.rx_ts1.eq(ts1_checker.detected),
self.rx_ts2.eq(ts2_checker.detected),