From 75c2eef7a8585cafbd62d5a1404ab6d7b2e15a90 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 13 Dec 2019 10:13:46 +0100 Subject: [PATCH] targets/serdes: cleanup and remove keep attributes (now directly added when applying constraints to signals --- kc705.py | 14 ++++++-------- pcie_screamer.py | 14 ++++++-------- usb3_pipe/serdes.py | 4 ---- versa_ecp5.py | 5 ++--- 4 files changed, 14 insertions(+), 23 deletions(-) diff --git a/kc705.py b/kc705.py index 17e4339..c25c5c7 100755 --- a/kc705.py +++ b/kc705.py @@ -64,24 +64,25 @@ _usb3_io = [ class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_oob = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_oob = ClockDomain() self.clock_domains.cd_clk125 = ClockDomain() # # # self.submodules.pll = pll = S7PLL(speedgrade=-2) pll.register_clkin(platform.request("clk200"), 200e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_oob, sys_clk_freq/8) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_oob, sys_clk_freq/8) pll.create_clkout(self.cd_clk125, 125e6) # USB3SoC ------------------------------------------------------------------------------------------ class USB3SoC(SoCMini): def __init__(self, platform, connector="pcie", with_etherbone=True, with_analyzer=True): + sys_clk_freq = int(125e6) - sys_clk_freq = int(156.5e6) + # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- @@ -106,9 +107,6 @@ class USB3SoC(SoCMini): self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints - self.crg.cd_sys.clk.attr.add("keep") - self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") - self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/156.5e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9/125e6) diff --git a/pcie_screamer.py b/pcie_screamer.py index 1cecc26..2bc4894 100755 --- a/pcie_screamer.py +++ b/pcie_screamer.py @@ -64,8 +64,8 @@ class Platform(XilinxPlatform): class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_oob = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_oob = ClockDomain() self.clock_domains.cd_clk125 = ClockDomain() # # # @@ -73,21 +73,19 @@ class _CRG(Module): clk100 = platform.request("clk100") platform.add_period_constraint(clk100, 1e9/100e6) - self.cd_sys.clk.attr.add("keep") - self.cd_clk125.clk.attr.add("keep") - self.submodules.pll = pll = S7PLL(speedgrade=-2) pll.register_clkin(clk100, 100e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_oob, sys_clk_freq/8) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_oob, sys_clk_freq/8) pll.create_clkout(self.cd_clk125, 125e6) # USB3SoC ------------------------------------------------------------------------------------------ class USB3SoC(SoCMini): def __init__(self, platform, with_analyzer=False): - sys_clk_freq = int(125e6) + + # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- diff --git a/usb3_pipe/serdes.py b/usb3_pipe/serdes.py index 178bd9f..93d4a40 100644 --- a/usb3_pipe/serdes.py +++ b/usb3_pipe/serdes.py @@ -358,8 +358,6 @@ class K7USB3SerDes(Module): ] # Timing constraints ----------------------------------------------------------------------- - gtx.cd_tx.clk.attr.add("keep") - gtx.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtx.cd_tx.clk, 1e9/gtx.tx_clk_freq) platform.add_period_constraint(gtx.cd_rx.clk, 1e9/gtx.rx_clk_freq) platform.add_false_path_constraints( @@ -458,8 +456,6 @@ class A7USB3SerDes(Module): ] # Timing constraints ----------------------------------------------------------------------- - gtp.cd_tx.clk.attr.add("keep") - gtp.cd_rx.clk.attr.add("keep") platform.add_period_constraint(gtp.cd_tx.clk, 1e9/gtp.tx_clk_freq) platform.add_period_constraint(gtp.cd_rx.clk, 1e9/gtp.rx_clk_freq) platform.add_false_path_constraints( diff --git a/versa_ecp5.py b/versa_ecp5.py index 09bd489..e971267 100755 --- a/versa_ecp5.py +++ b/versa_ecp5.py @@ -87,8 +87,9 @@ class _CRG(Module): class USB3SoC(SoCMini): def __init__(self, platform, connector="pcie", with_etherbone=False, with_analyzer=False): - sys_clk_freq = int(125e6) + + # SoCMini ---------------------------------------------------------------------------------- SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True) # CRG -------------------------------------------------------------------------------------- @@ -116,8 +117,6 @@ class USB3SoC(SoCMini): self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints - self.eth_phy.crg.cd_eth_rx.clk.attr.add("keep") - self.eth_phy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9/125e6)