FPGA/usb3_pipe
1
0
Fork 0
mirror of https://github.com/enjoy-digital/usb3_pipe.git synced 2025-01-04 10:18:41 +08:00
Code Issues Projects Releases Wiki Activity

training: connect rx_ts signals

Browse Source
This commit is contained in:
Florent Kermarrec 2019-10-08 13:07:26 +02:00
parent 7bfd22de78
commit 7a31882f38
1 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
usb3_pipe/training.py
View File

@ -189,15 +189,17 @@ class TSUnit(Module):
# # #
# Ordered Set Checkers ---------------------------------------------------------------------
tseq_checker = TSChecker(ordered_set=TSEQ, n_ordered_sets=8)
ts1_checker = TSChecker(ordered_set=TS1, n_ordered_sets=8)
ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.submodules += tseq_checker, ts1_checker, ts2_checker
self.submodules.tseq_checker = tseq_checker = TSChecker(ordered_set=TSEQ, n_ordered_sets=8)
self.submodules.ts1_checker = ts1_checker = TSChecker(ordered_set=TS1, n_ordered_sets=8)
self.submodules.ts2_checker = ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.comb += [
serdes.source.ready.eq(self.rx_enable),
serdes.source.connect(tseq_checker.sink, omit={"ready"}),
serdes.source.connect(ts1_checker.sink, omit={"ready"}),
serdes.source.connect(ts2_checker.sink, omit={"ready"}),
serdes.source.ready.eq(self.rx_enable),
self.rx_tseq.eq(tseq_checker.detected),
self.rx_ts1.eq(ts1_checker.detected),
self.rx_ts2.eq(ts2_checker.detected),
]
# Ordered Set Generators -------------------------------------------------------------------