FPGA/usb3_pipe
1
0
Fork 0
mirror of https://github.com/enjoy-digital/usb3_pipe.git synced 2025-01-04 10:18:41 +08:00
Code Issues Projects Releases Wiki Activity

versa_ecp5: reduce sys_clk_freq to 125MHz (synchronous with the 250MHz tx clk since generated from the same clk source)

Browse Source
This commit is contained in:
Florent Kermarrec 2019-12-09 18:04:30 +01:00
parent b553eb3185
commit 7bdd251c02
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
versa_ecp5.py
View File

@ -88,7 +88,7 @@ class _CRG(Module):
class USB3SoC(SoCMini):
def __init__(self, platform, connector="pcie", with_etherbone=False, with_analyzer=False):
sys_clk_freq = int(150e6)
sys_clk_freq = int(125e6)
SoCMini.__init__(self, platform, sys_clk_freq, ident="USB3SoC", ident_version=True)
# CRG --------------------------------------------------------------------------------------