diff --git a/test/test_scrambling.py b/test/test_scrambling.py
index f45ed67..5a13a72 100644
--- a/test/test_scrambling.py
+++ b/test/test_scrambling.py
@@ -5,7 +5,7 @@ import unittest
 
 from migen import *
 
-from usb3_pipe.scrambling import Scrambler
+from usb3_pipe.scrambling import Scrambler, Descrambler
 
 scrambler_ref = [
     0x8dbf6dbe, 0xe6a740be, 0xb2e2d32c, 0x2a770207,
@@ -26,7 +26,7 @@ scrambler_ref = [
     0xd514af76, 0xb660ac4f, 0xb762d679, 0x2ae5e743
 ]
 
-class TestScrambler(unittest.TestCase):
+class TestScrambling(unittest.TestCase):
     def test_scrambler_data(self):
         def generator(dut):
             yield dut.source.ready.eq(1)
@@ -55,3 +55,28 @@ class TestScrambler(unittest.TestCase):
 
         dut = Scrambler()
         run_simulation(dut, generator(dut))
+
+    def test_descrambler_data(self):
+        def generator(dut):
+            for i in range(16):
+                yield dut.sink.valid.eq(1)
+                yield dut.sink.data.eq(0)
+                yield
+            for i in range(16):
+                yield dut.sink.valid.eq(1)
+                yield dut.sink.data.eq(scrambler_ref[i])
+                yield
+            yield dut.sink.valid.eq(0)
+            for i in range(64):
+                yield
+
+        def checker(dut):
+            yield dut.source.ready.eq(1)
+            while (yield dut.source.valid) == 0:
+                yield
+            for i in range(16):
+                self.assertEqual((yield dut.source.data), 0)
+                yield
+
+        dut = Descrambler()
+        run_simulation(dut, [generator(dut), checker(dut)], vcd_name="toto.vcd")
\ No newline at end of file
diff --git a/usb3_pipe/scrambling.py b/usb3_pipe/scrambling.py
index e74948a..fd3784a 100644
--- a/usb3_pipe/scrambling.py
+++ b/usb3_pipe/scrambling.py
@@ -77,7 +77,6 @@ class ScramblerUnit(Module):
 
 class Scrambler(Module):
     def __init__(self):
-        self.enable = Signal(reset=1)
         self.sink   =   sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
         self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
 
@@ -89,21 +88,17 @@ class Scrambler(Module):
         self.comb += sink.connect(source)
         for i in range(4):
             self.comb += [
-                If(self.enable,
-                    If(sink.ctrl[i], # K codes shall not be scrambled.
-                        source.data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)])
-                    ).Else(
-                        source.data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)] ^ scrambler.value[8*i:8*(i+1)])
-                    )
+                If(sink.ctrl[i], # K codes shall not be scrambled.
+                    source.data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)])
+                ).Else(
+                    source.data[8*i:8*(i+1)].eq(sink.data[8*i:8*(i+1)] ^ scrambler.value[8*i:8*(i+1)])
                 )
             ]
 
-
 # Descrambler (Scrambler + Auto-Synchronization) ---------------------------------------------------
 
 class Descrambler(Module):
     def __init__(self):
-        self.enable = Signal(reset=1)
         self.sink   =   sink = stream.Endpoint([("data", 32), ("ctrl", 4)])
         self.source = source = stream.Endpoint([("data", 32), ("ctrl", 4)])
 
@@ -112,13 +107,12 @@ class Descrambler(Module):
         scrambler = Scrambler()
         self.submodules += scrambler
 
-        sync   = Signal()
-        synced = Signal()
-        self.comb += sync.eq(sink.data == scrambler.source.data)
-        self.sync += If(sync, synced.eq(1))
+        synchro      = Signal()
+        synchronized = Signal()
+        self.comb += synchro.eq(sink.valid & sink.ready & (scrambler.source.data == 0x00000000))
+        self.sync += If(synchro, synchronized.eq(1))
         self.comb += [
-            sink.ready.eq(1),
             sink.connect(scrambler.sink),
-            scrambler.sink.valid.eq(sink.valid & (sync | synced)),
+            scrambler.sink.valid.eq(sink.valid & (synchro | synchronized)),
             scrambler.source.connect(source)
         ]