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training: add enable signals

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This commit is contained in:
Florent Kermarrec 2019-10-08 12:12:40 +02:00
parent b138f0fc2e
commit 8a876f9414
2 changed files with 18 additions and 8 deletions
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10
usb3_pipe/ltssm.py
View File

@ -181,7 +181,9 @@ class PollingFSM(FSM):
self.act("LFPS",
serdes.rx_align.eq(1),
lfps_unit.tx_polling.eq(1),
NextState("RX-EQ"), # LFPS handshake.
If(lfps_unit.rx_polling,
NextState("RX-EQ"), # LFPS handshake.
),
#self.exit_to_compliance_mode.eq(1), # First LFPS timeout.
#self.exit_to_ss_disabled.eq(1), # Subsequent LFPS timeouts (Dev) or directed (DS).
#self.exit_to_rx_detect.eq(1), # Subsequent LFPS timeouts (DS).
@ -191,6 +193,8 @@ class PollingFSM(FSM):
# RxEQ State -------------------------------------------------------------------------------
self.act("RX-EQ",
serdes.rx_align.eq(1),
lfps_unit.tx_polling.eq(1),
ts_unit.rx_enable.eq(1),
If(ts_unit.rx_tseq,
NextState("ACTIVE"), # TSEQ transmitted.
),
@ -200,6 +204,7 @@ class PollingFSM(FSM):
# Active State -----------------------------------------------------------------------------
self.act("ACTIVE",
ts_unit.rx_enable.eq(1),
If(ts_unit.rx_ts1 | ts_unit.rx_ts2,
NextState("CONFIGURATION"), # 8 consecutiive TS1 or TS2 received.
),
@ -210,6 +215,8 @@ class PollingFSM(FSM):
# Configuration State ----------------------------------------------------------------------
self.act("CONFIGURATION",
ts_unit.rx_enable.eq(1),
ts_unit.tx_enable.eq(1),
ts_unit.tx_ts2.eq(1),
If(ts_unit.rx_ts2,
NextState("IDLE"), # TS2 handshake.
@ -248,7 +255,6 @@ class LTSSM(Module):
serdes = serdes,
lfps_unit = lfps_unit,
ts_unit = ts_unit)
self.comb += self.polling_fsm.reset.eq(lfps_unit.rx_polling)
# LTSSM FSM --------------------------------------------------------------------------------
self.submodules.ltssm_fsm = LTSSMFSM()

16
usb3_pipe/training.py
View File

@ -177,10 +177,13 @@ class TSGenerator(Module):
class TSUnit(Module):
def __init__(self, serdes):
self.rx_tseq = Signal() # o
self.rx_ts1 = Signal() # o
self.rx_ts2 = Signal() # o
self.tx_ts2 = Signal() # i
self.rx_enable = Signal() # i
self.rx_tseq = Signal() # o
self.rx_ts1 = Signal() # o
self.rx_ts2 = Signal() # o
self.tx_enable = Signal() # i
self.tx_ts2 = Signal() # i
# # #
@ -190,6 +193,7 @@ class TSUnit(Module):
ts2_checker = TSChecker(ordered_set=TS2, n_ordered_sets=8)
self.submodules += tseq_checker, ts1_checker, ts2_checker
self.comb += [
serdes.source.ready.eq(self.rx_enable),
serdes.source.connect(tseq_checker.sink, omit={"ready"}),
serdes.source.connect(ts1_checker.sink, omit={"ready"}),
serdes.source.connect(ts2_checker.sink, omit={"ready"}),
@ -199,8 +203,8 @@ class TSUnit(Module):
ts2_generator = TSGenerator(ordered_set=TS2, n_ordered_sets=8)
self.submodules += ts2_generator
self.comb += [
If(self.tx_ts2,
ts2_generator.send.eq(1),
If(self.tx_enable,
ts2_generator.send.eq(self.tx_ts2),
ts2_generator.source.connect(serdes.sink),
)
]