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pocs/kc705: TS2 received by Host and FPGA

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This commit is contained in:
Florent Kermarrec 2019-10-04 13:11:36 +02:00
parent a1eb6c73ab
commit 8bb9821a61
3 changed files with 19 additions and 10 deletions
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17
pocs/kc705/kc705.py
View File

@ -129,8 +129,10 @@ class USB3SoC(SoCMini):
gtx.add_stream_endpoints()
gtx.add_controls()
self.add_csr("gtx")
gtx._tx_enable.storage.reset = 1 # Enabled by default
gtx._rx_enable.storage.reset = 1 # Enabled by default
gtx._tx_enable.storage.reset = 1 # Enabled by default
gtx._rx_enable.storage.reset = 1 # Enabled by default
gtx._tx_polarity.storage.reset = 1
gtx._rx_polarity.storage.reset = 1
self.submodules += gtx
# timing constraints
@ -191,7 +193,7 @@ class USB3SoC(SoCMini):
self.submodules += ts2_receiver
# TS2 Transmitter --------------------------------------------------------------------------
ts2_transmitter = OrderedSetTransmitter(ordered_set=TS2, n_ordered_sets=32768, data_width=32)
ts2_transmitter = OrderedSetTransmitter(ordered_set=TS2, n_ordered_sets=1024, data_width=32)
ts2_transmitter = ClockDomainsRenamer("tx")(ts2_transmitter)
self.submodules += ts2_transmitter
@ -237,9 +239,10 @@ class USB3SoC(SoCMini):
)
fsm.act("SEND-TS2-WAIT-TS2",
gtx.rx_align.eq(0),
ts2_send_sync.i.eq(ts2_done),
gtx.source.connect(ts2_receiver.sink),
ts2_transmitter.source.connect(gtx.sink),
If(ts2_done & ts2_det_sync.o,
If(ts2_det_sync.o,
NextState("READY")
)
)
@ -281,7 +284,11 @@ class USB3SoC(SoCMini):
ts1_receiver.detected,
ts1_receiver.reset,
ts1_receiver.loopback,
ts1_receiver.scrambling
ts1_receiver.scrambling,
ts2_receiver.detected,
ts2_receiver.reset,
ts2_receiver.loopback,
ts2_receiver.scrambling
]
self.submodules.rx_analyzer = LiteScopeAnalyzer(analyzer_signals, 4096, clock_domain="rx", csr_csv="rx_analyzer.csv")
self.add_csr("rx_analyzer")

11
pocs/kc705/test_rx_analyzer.py
View File

@ -6,7 +6,7 @@ import time
from litex import RemoteClient
from litescope import LiteScopeAnalyzerDriver
from usb3_pipe.common import TSEQ, TS1
from usb3_pipe.common import TSEQ, TS1, TS2
wb = RemoteClient()
wb.open()
@ -15,7 +15,6 @@ wb.open()
TSEQ_FIRST_WORD = int.from_bytes(TSEQ.to_bytes()[0:4], byteorder="little")
TS1_FIRST_WORD = int.from_bytes(TS1.to_bytes()[0:4], byteorder="little")
print("%08x" %TS1_FIRST_WORD)
# FPGA ID ------------------------------------------------------------------------------------------
fpga_id = ""
@ -41,11 +40,13 @@ analyzer.configure_subsampler(1)
#analyzer.configure_trigger(cond={
# "soc_gtx0_source_payload_ctrl": 0b0001,
# "soc_gtx0_source_payload_data": TSEQ_FIRST_WORD})
analyzer.configure_trigger(cond={
"soc_gtx0_source_payload_ctrl": 0b1111,
"soc_gtx0_source_payload_data": TS1_FIRST_WORD})
#analyzer.configure_trigger(cond={
# "soc_gtx0_source_payload_ctrl": 0b1111,
# "soc_gtx0_source_payload_data": TS1_FIRST_WORD})
#analyzer.configure_trigger(cond={"soc_tseq_receiver_detected": 1})
#analyzer.configure_trigger(cond={"soc_ts1_receiver_detected": 1})
#analyzer.configure_trigger(cond={"soc_ts2_receiver_detected": 1})
analyzer.configure_trigger(cond={})
analyzer.run(offset=32, length=4096)
analyzer.wait_done()
analyzer.upload()

1
pocs/kc705/test_tx_analyzer.py
View File

@ -36,6 +36,7 @@ while (wb.regs.gtx_rx_ready.read() == 0):
analyzer = LiteScopeAnalyzerDriver(wb.regs, "tx_analyzer", debug=True)
analyzer.configure_subsampler(1)
analyzer.configure_trigger(cond={"soc_gtx0_sink_valid": 1})
analyzer.configure_trigger(cond={})
analyzer.run(offset=32, length=4096)
analyzer.wait_done()
analyzer.upload()